Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths - researchr publication

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Ravi Kanth Uppu, Ravi Tej Uppu, Adit D. Singh, Ilia Polian. Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014. pages 133-138, IEEE, 2014. [doi]

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