Table of Contents

• Tutorial T1: Neuromorphic Computing - Algorithms, Devices and SystemsBipin Rajendran, Udaya S. Ganguly, Manan Suri. 1-2 [doi]
• Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded SystemsPrabhat Mishra, Swarup Bhunia, Srivaths Ravi. 3-5 [doi]
• Tutorial T3: Error Resilient Real-Time Embedded Systems: Computing, Communications and ControlJacob A. Abraham, Abhijit Chatterjee. 6-7 [doi]
• Tutorial T4: MEMS: Design, Fabrication, and their Applications as Chemical and BiosensorsNitin S. Kale. 8-9 [doi]
• Tutorial T5: High Performance Low Power Designs - Challenges and Best practices in Design, Verification and TestNagesh Tamarapalli, Prashanth Vallur, Sachin Kulkarni. 10-11 [doi]
• Tutorial T6: FinFET Device Circuit Co-design: Issues and ChallengesSudeb Dasgupta, Bulusu Anand. 12-13 [doi]
• Tutorial T7: Physically Unclonable Function: A Promising Security Primitive for Internet of ThingsDebdeep Mukhopadhyay, Rajat Subhra Chakraborty, Phuong Ha Nguyen, Durga Prasad Sahoo. 14-15 [doi]
• Tutorial T8: Scheduling Issues in Embedded Real-Time SystemsParmesh Ramanathan. 16 [doi]
• Tutorial T9: Dealing with Startup Issues in Low Power Mixed Signal SoCsSriram Ganesan. 17-18 [doi]
• Embedded Tutorial ET1: Better-than-Worst-Case Timing DesignsAdit D. Singh. 19-20 [doi]
• Embedded Tutorial ET2: Volume Diagnosis for Yield ImprovementWu-Tung Cheng, Sudhakar M. Reddy. 21-23 [doi]
• Invited Talk: IoT Protocols War and the Way ForwardVirendra Gupta, Jayaraghavendran. 28 [doi]
• ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGAJude Angelo Ambrose, Tuo Li 0001, Daniel Murphy, Shivam Gargg, Nick Higgins, Sri Parameswaran. 29-34 [doi]
• Parameterizable FPGA Framework for Particle Filter Based Object Tracking in VideoPinalkumar Engineer, Rajbabu Velmurugan, Sachin Patkar. 35-40 [doi]
• RELSPEC: A Framework for Early Reliability Refinement of Embedded ApplicationsSaurav Kumar Ghosh, Aritra Hazra, Soumyajit Dey. 41-46 [doi]
• Thermal Extension of the Total Bandwidth ServerRehan Ahmed, Ayoosh Bansal, Bhuvana Kakunoori, Parameswaran Ramanathan, Kewal K. Saluja. 47-52 [doi]
• Thermal-Aware Test Data Compression Using Dictionary Based CodingRajit Karmakar, Santanu Chattopadhyay. 53-58 [doi]
• CERI: Cost-Effective Routing Implementation Technique for Network-on-ChipRimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, Radi Husin Bin Ramlee, Mark Zwolinski. 59-64 [doi]
• Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded ProcessorsNeethu Bal Mallya, Geeta Patil, Biju K. Raveendran. 65-70 [doi]
• A Frequency Scan Scheme for PLL-Based Locking to High-Q MEMS ResonatorsAnjan Kumar, Abhinav Dikshit, Bill Clark, Jeff Yan. 71-74 [doi]
• NFC for Pervasive Healthcare MonitoringT. V. Prabhakar, Ujwal Mysore, Uday Saini, K. J. Vinoy, Bharadwaj Amruthur. 75-80 [doi]
• Hardware Solution for Real-Time Face RecognitionGopinath Mahale, Hamsika Mahale, Arnav Goel, S. K. Nandy, S. Bhattacharya, Ranjani Narayan. 81-86 [doi]
• Towards a Real-Time Campus-Scale Water Balance Monitoring SystemVignesh D. Kudva, Prashanth Nayak, Alok Rawat, Anjana G. Ry, K. R. Sheetal Kumar, Bharadwaj Amrutur, Mohan Kumar M. Sy. 87-92 [doi]
• Robot Navigation Using Neuro-electronic Hybrid SystemsJude Baby George, Grace Mathew Abraham, Bharadwaj Amrutur, Sujit Kumar Sikdar. 93-98 [doi]
• Comparison of Off-Chip Training Methods for Neuromemristive SystemsCory E. Merkel, Dhireesha Kudithipudi. 99-104 [doi]
• OcNoC: Efficient One-Cycle Router Implementation for 3D Mesh Network-on-ChipRamon Fernandes, Lucas Brahm, Thais Webber, Rodrigo Cataldo, Leticia B. Poehls, César A. M. Marcon. 105-110 [doi]
• Mode-Division-Multiplexed Photonic Router for High Performance Network-on-ChipDharanidhar Dang, Biplab Patra, Rabi N. Mahapatra, Martin Fiers. 111-116 [doi]
• A Hardware and Thermal Analysis of DVFS in a Multi-core System with Hybrid WNoC ArchitectureGade Narayana Sri Harsha, Hemanta Kumar Mondal, Sujay Deb. 117-122 [doi]
• Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-clockwise Optical RoutingMatthew Kennedy, Avinash Karanth Kodi. 123-128 [doi]
• Effects of Nondeterminism in Hardware and Software Simulation with Thread MappingGiordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead, Ankit More. 129-134 [doi]
• Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and SimulationSiddharth Nilakantan, Scott Lerner, Mark Hempstead, Baris Taskin. 135-140 [doi]
• Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPsShirshendu Das, Hemangee K. Kapoor. 141-146 [doi]
• Cross-Layer Exploration of Heterogeneous Multicore Processor ConfigurationsSantanu Sarma, Nikil Dutt. 147-152 [doi]
• Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR FactorizationsFarhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna C, Nalesh Sivanandan, Nandhini Gopalan, Soumyendu Raha, S. K. Nandy, Ranjani Narayan. 153-158 [doi]
• On-the-Fly Donut Formation in Compiled MemoryDarvinder Singh, Isha Garg, Vineet Sachan, Prasanna Nalawar. 159-163 [doi]
• Scaling the UVM_REG Model towards Automation and Simplicity of UseAbhishek Jain 0002, Richa Gupta. 164-169 [doi]
• On the Analysis of Reversible Booth's MultiplierJakia Sultana, Sajib Kumar Mitra, Ahsan Raja Chowdhury. 170-175 [doi]
• Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMsM. Sultan M. Siddiqui, Shailendra Sharad, Yogendra Sharma, Amit Khanuja. 176-180 [doi]
• A CMOS 90nm 50Mhz Supply Noise Tolerant High Density 8T-NAND ROMKedar Janardan Dhori, Vinay Kumar, Ashish Kumar. 181-185 [doi]
• 2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple GridsNitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala. 186-191 [doi]
• Formal Methods for Pattern Based Reliability Analysis in Embedded SystemsSumana Ghosh, Pallab Dasgupta. 192-197 [doi]
• On Event Driven Modeling of Continuous Time SystemsDushyant Juneja. 198-203 [doi]
• A Novel CKE-ODT-CSN Encoding Scheme in DDR Memory InterfaceVinod Inipodu Murugan, Narayanan Mayandi, Arul Sendhil. 204-208 [doi]
• A Design Approach for Compressor Based Approximate MultipliersNaman Maheshwari, Zhixi Yang, Jie Han, Fabrizio Lombardi. 209-214 [doi]
• Integrated 16-Channel Transmit and Receive Beamforming ASIC for Ultrasound ImagingChandrashekar Dusa, Samiyuktha Kalalii, P. Rajalakshmi, Omkeshwar Rao. 215-220 [doi]
• Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded ArchitecturesKarthik Swaminathan, Jagadish Kotra, Huichu Liu, Jack Sampson, Mahmut T. Kandemir, Vijaykrishnan Narayanan. 221-226 [doi]
• Exploring Scope of Power Reduction with Constrained Physical SynthesisKaustav Guha, Sourav Saha, Ricardo Nigaglioni. 227-231 [doi]
• All Optical Implementation of Mach-Zehnder Interferometer Based Reversible Sequential CountersPratik Dutta, Chandan Bandyopadhyay, Hafizur Rahaman. 232-237 [doi]
• Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic ProgrammingNusrat Jahan Lisa, Hafiz Md. Hasan Babu. 238-243 [doi]
• On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode FeedbackK. S. Rakshitdatta, Nagendra Krishnapura. 244-248 [doi]
• Accurate Constant Transconductance Generation without Off-Chip ComponentsImon Mondal, Nagendra Krishnapura. 249-253 [doi]
• Ultra-fast Cap-less LDO for Dual Lane USB in 28FDSOISaurabh Kumar Singh, Gautam Dey Kanungo. 254-259 [doi]
• Any Capacitor Stable LVR Using Sub-unity Gain Positive Feedback Loop in 65nm CMOSSaurabh Kumar Singh, Nitin Bansal. 260-264 [doi]
• A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing ApplicationT. Rahul, Bibhudatta Sahoo, S. Arya, S. J. Parvathy, Veeresh Babu Vulligaddala. 265-270 [doi]
• A Wide Tuning Range LC Quadrature Phase Oscillator Employing Mode SwitchingSivaramakrishna Rudrapati, Sharayu Jagtap, M. Umar Shaikh, Shalabh Gupta. 271-275 [doi]
• Block-Level Electro-Migration Analysis (BEMA) for Safer Product LifeRadhika Gupta, Atul Bhargava, Rakeshshenoy Panemangalore. 276-281 [doi]
• Recessed MOSFET in 28 nm FDSOI for Better Breakdown CharacteristicsN. K. Kranthi, Radhakrishnan Sithanandam, Rama Komaragiri. 282-285 [doi]
• A Noise Aware CML Latch Modelling for Large System SimulationDebesh Bhatta, Suvadeep Banerjee, Abhijit Chatterjee. 286-291 [doi]
• Design of High Speed Ternary Full Adder and Three-Input XOR Circuits Using CNTFETsSneh Lata Murotiya, Anu Gupta. 292-297 [doi]
• An Efficient Transition Detector Exploiting Charge SharingYu Wang, Adit D. Singh. 298-303 [doi]
• A High-Efficiency Switched-Capacitance HTFET Charge Pump for Low-Input-Voltage ApplicationsUnsuk Heo, Xueqing Li, Huichu Liu, Sumeet Kumar Gupta, Suman Datta, Vijaykrishnan Narayanan. 304-309 [doi]
• Power Optimization Techniques for DDR3 SDRAMPreeti Ranjan Panda, Vishal Patel, Praxal Shah, Namita Sharma, Vaidyanathan Srinivasan, Dipankar Sarma. 310-315 [doi]
• A Novel Ternary Content-Addressable Memory (TCAM) Design Using Reversible LogicS. Dinesh Kumar, Sk. Noor Mahammad. 316-320 [doi]
• Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data CircuitsGuilherme Heck, Leandro S. Heck, Ajay Singhvi, Matheus T. Moreira, Peter A. Beerel, Ney Laert Vilar Calazans. 321-326 [doi]
• Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 FiltersPramod Kumar Meher, Basant Kumar Mohanty, M. N. S. Swamy. 327-332 [doi]
• SPAA-Aware 2D Gaussian Smoothing Filter Design Using Efficient Approximation TechniquesAnkur Jaiswal, Bharat Garg, Vikas Kaushal, G. K. Sharma. 333-338 [doi]
• An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing ApplicationsJ. G. Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan. 339-344 [doi]
• FPGA Based Scalable Fixed Point QRD Core Using Dynamic Partial ReconfigurationGayathri R. Prabhu, Bibin Johnson, J. Sheeba Rani. 345-350 [doi]
• A High-Performance Energy-Efficient Hybrid Redundant MAC for Error-Resilient ApplicationsSunil Dutt, Anshu Chauhan, Rahul Bhadoriya, Sukumar Nandi, Gaurav Trivedi. 351-356 [doi]
• Energy Aware Computation Driven Approximate DCT Architecture for Image ProcessingVikas Kaushal, Bharat Garg, Ankur Jaiswal, G. K. Sharma. 357-362 [doi]
• New Methods for Simulation Speed-up and Test Qualification with Analog Fault SimulationV. R. Devanathan, Lakshmanan Balasubramanian, Rubin A. Parekhji. 363-368 [doi]
• Efficient Peak Power Estimation Using Probabilistic Cost-Benefit AnalysisHadi Hajimiri, Kamran Rahmani, Prabhat Mishra. 369-374 [doi]
• DFT Technique for Quick Characterization of Flash Offset in Pipeline ADCsPradeep Nair, Nagarajan Viswanathan. 375-380 [doi]
• Framework for Selective Flip-Flop Replacement for Soft Error MitigationPavan Vithal Torvi, V. R. Devanathan, V. Kamakoti. 381-386 [doi]
• Diagnostic Tests for Pre-bond TSV DefectsBei Zhang, Vishwani D. Agrawal. 387-392 [doi]
• Few Good Frequencies for Power-Constrained TestSindhu Gunasekar, Vishwani D. Agrawal. 393-398 [doi]
• Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic CircuitsXijiang Lin, Sudhakar M. Reddy, Janusz Rajski. 399-404 [doi]
• Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMsFelipe Lavratti, Letícia Maria Bolzani Poehls, Fabian Vargas, Andrea Calimera, Enrico Macii. 405-410 [doi]
• Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write PerformanceGaurav Narang, Pragya Sharma, Mansi Jain, Anuj Grover. 411-416 [doi]
• A Recursive Model for Smooth Approximation to Wirelength and Its Impact on Analytical PlacementB. N. B. Ray, Shankar Balachandran. 417-422 [doi]
• A Nonlinear Analytical Optimization Method for Standard Cell Placement of VLSI CircuitsSameer Pawanekar, Gaurav Trivedi, Kalpesh Kapoor. 423-428 [doi]
• Monitoring AMS Simulation: From Assertions to FeaturesAntara Ain, Pallab Dasgupta. 429-434 [doi]
• BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer CircuitsEleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler. 435-440 [doi]
• Optimized Logarithmic Barrel Shifter in Reversible Logic SynthesisSajib Kumar Mitra, Ahsan Raja Chowdhury. 441-446 [doi]
• Rectilinear Steiner Clock Tree Routing Technique with Buffer Insertion in Presence of ObstaclesPartha Pratim Saha, Sumonto Saha, Tuhina Samanta. 447-451 [doi]
• Geometric Programming Formulation for Gate Sizing with Pipelining ConstraintsSrinath R. Naidu. 452-457 [doi]
• On-the-Fly Mapping for Synthesizing Dynamic Domino CircuitsSai Praveen Kadiyala, Debasis Samanta. 458-463 [doi]
• FirmLeak: A Framework for Efficient and Accurate Runtime Estimation of Leakage Power by FirmwareArun Joseph, Anand Haridass, Charles Lefurgy, Spandana Rachamalla, Sreekanth Pai, Diyanesh Chinnakkonda, Vidushi Goyal. 464-469 [doi]
• Design of 3D Antennas for 24 GHz ISM Band ApplicationsPutluru Sravani, Madhav Rao. 470-474 [doi]
• Smart Port Allocation for Adaptive NoC RoutersReenu James, John Jose, Jobin K. Antony. 475-480 [doi]
• EvoDeb: Debugging Evolving Hardware DesignsDebjyoti Bhattacharjee, Ansuman Banerjee, Anupam Chattopadhyay. 481-486 [doi]
• Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power ConstraintsSpencer K. Millican, Kewal K. Saluja. 487-492 [doi]
• A 300 KBPS 23.2 MHz Binary Frequency Shift Keying Transmitter for USB Power Line Communication in 180 nm BiCMOSAswin Srinivasa Rao, Karthik Subburaj. 493-498 [doi]
• A Methodology for Placement of Regular and Structured CircuitsSuman Chatterjee, Vikram Singh Saun, Anand Arunachalam 0001. 499-504 [doi]
• A Flexible Scalable Hardware Architecture for Radial Basis Function Neural NetworksMahnaz Mohammadi, Nitin Satpute, Rohit Ronge, Jayesh R. Chandiramani, S. K. Nandy, Aamir Raihan, Tanmay Verma, Ranjani Narayan, Sukumar Bhattacharya. 505-510 [doi]
• Sensitivity Analysis Based Predictive Modeling for MPSoC Performance and Energy EstimationHongwei Wang, Ziyuan Zhu, Jinglin Shi, Yongtao Su. 511-516 [doi]
• Accelerating SVM on Ultra Low Power ASIP for High Throughput Streaming ApplicationsAnmol Gupta, Ashutosh Pal. 517-522 [doi]
• Implementation of NOR Logic Based on Material Implication on CMOL FPGA ArchitecturePravin Mane, Nishil Talati, Ameya Riswadkar, Bhavan Jasani, C. K. Ramesha. 523-528 [doi]
• Analysis of Second-Order Effect Components of Drain Conductance and Its Implication on Output Resistance of Wilson Current MirrorKirmender Singh, A. B. Bhattacharyya. 529-534 [doi]
• Noninvasive Cuffless Blood Pressure Measurement by Vascular Transit TimeSatya Narayan Shukla, Karan Kakwani, Amit Patra, Bipin Kumar Lahkar, Vivek Kumar Gupta, Alwar Jayakrishna, Puneet Vashisht, Induja Sreekanth. 535-540 [doi]
• Reliability Enhancement of SoCs Based on Dynamic Memory Access Profiling in Conjunction with PVT MonitoringDeepak Baranwal, Digvijay Singh, Khanusiya Soyeb, Sidhartha Sankar Rout, Sujay Deb. 541-546 [doi]
• DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAsMuhammad Adeel Tajammul, Syed M. A. H. Jafri, Peeter Ellervee, Ahmed Hemani, Hannu Tenhunen, Juha Plosila. 547-552 [doi]