Embedded Tutorial ET1: Better-than-Worst-Case Timing Designs

Adit D. Singh. Embedded Tutorial ET1: Better-than-Worst-Case Timing Designs. In 28th International Conference on VLSI Design, VLSID 2015, Bangalore, India, January 3-7, 2015. pages 19-20, IEEE Computer Society, 2015. [doi]

Abstract

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