Abstract is missing.
- Ambient variation-tolerant and inter components aware thermal management for mobile system on chipsFrancesco Paterna, Joe Zanotelli, Tajana Simunic Rosing. 1-6 [doi]
- A smaller and faster variant of RSMNoritaka Yamashita, Kazuhiko Minematsu, Toshihiko Okamura, Yukiyasu Tsunoo. 1-6 [doi]
- Application of Mission Profiles to enable cross-domain constraint-driven designC. Katzschke, M.-P. Sohn, Markus Olbrich, Volker Meyer zu Bexten, Markus Tristl, Erich Barke. 1-6 [doi]
- Improving hamiltonian-based routing methods for on-chip networks: A turn model approachPoona Bahrebar, Dirk Stroobandt. 1-4 [doi]
- Package geometric aware thermal analysis by infrared-radiation thermal imagesJui-Hung Chien, Hao Yu, Ruei-Siang Hsu, Hsueh-Ju Lin, Shih-Chieh Chang. 1-4 [doi]
- Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refreshMohammadSadegh Sadri, Matthias Jung 0001, Christian Weis, Norbert Wehn, Luca Benini. 1-4 [doi]
- Energy-efficient FPGA implementation for binomial option pricing using OpenCLValentin Mena Morales, Pierre-Henri Horrein, Amer Baghdadi, Erik Hochapfel, Sandrine Vaton. 1-6 [doi]
- A multi banked - Multi ported - Non blocking shared L2 cache for MPSoC platformsIgor Loi, Luca Benini. 1-6 [doi]
- Energy efficient in-memory AES encryption based on nonvolatile domain-wall nanowireYuhao Wang, Hao Yu, Dennis Sylvester, Pingfan Kong. 1-4 [doi]
- Cross-correlation of specification and RTL for soft IP analysisBhanu Pratap Singh, Arunprasath Shankar, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, Steve Clay. 1-6 [doi]
- Empowering study of delay bound tightness with simulated annealingXueqian Zhao, Zhonghai Lu. 1-6 [doi]
- GPGPUs: How to combine high computational power with high reliabilityLeonardo Arturo Bautista Gomez, Franck Cappello, Luigi Carro, Nathan DeBardeleben, B. Fang, Sudhanva Gurumurthi, K. Pattabiraman, Paolo Rech, Matteo Sonza Reorda. 1-9 [doi]
- Design of 3D nanomagnetic logic circuits: A full-adder case studyRobert Perricone, Xiaobo Sharon Hu, Joseph Nahas, Michael T. Niemier. 1-6 [doi]
- Hybrid side-channel/machine-learning attacks on PUFs: A new threat?Xiaolin Xu, Wayne Burleson. 1-6 [doi]
- Design and evaluation of fine-grained power-gating for embedded microprocessorsMasaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura. 1-6 [doi]
- System integration - The bridge between More than Moore and More MooreAndy Heinig, Manfred Dietrich, Andreas Herkersdorf, Felix Miller, Thomas Wild, Kai Hahn, Armin Grunewald, Rainer Brück, Steffen Krohnert, Jochen Reisinger. 1-9 [doi]
- Aging-aware standard cell library designSaman Kiamehr, Farshad Firouzi, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori. 1-4 [doi]
- Reliability-Aware Exceptions: Tolerating intermittent faults in microprocessor array structuresWaleed Dweik, Murali Annavaram, Michel Dubois. 1-6 [doi]
- Automatic generation of custom SIMD instructions for Superword Level ParallelismTaemin Kim, Yatin Hoskote. 1-6 [doi]
- Providing regulation services and managing data center peak power budgetsBaris Aksanli, Tajana Rosing. 1-4 [doi]
- On the correctness, optimality and precision of Static Probabilistic Timing AnalysisSebastian Altmeyer, Robert I. Davis. 1-6 [doi]
- Design and fabrication of a 315 μΗ bondwire micro-transformer for ultra-low voltage energy harvestingEnrico Macrelli, Ningning Wang, Saibal Roy, Michael Hayes, Rudi Paolo Paganelli, Marco Tartagni, Aldo Romani. 1-4 [doi]
- Combined DVFS and mapping exploration for lifetime and soft-error susceptibility improvement in MPSoCsAnup Das 0001, Akash Kumar, Bharadwaj Veeravalli, Cristiana Bolchini, Antonio Miele. 1-6 [doi]
- Non-intrusive integration of advanced diagnosis features in automotive E/E-architecturesUlrich Abelein, Alejandro Cook, Piet Engelke, Michael Glaß, Felix Reimann, Laura Rodriguez Gomez, Thomas Russ, Jürgen Teich, Dominik Ull, Hans-Joachim Wunderlich. 1-6 [doi]
- Exploring the limits of phase change memoriesMatthias Wuttig. 1-2 [doi]
- PSP-Cache: A low-cost fault-tolerant cache memory architectureHamed Farbeh, Seyed Ghassem Miremadi. 1-4 [doi]
- The schedulability region of two-level mixed-criticality systems based on EDF-VDDirk Muller, Alejandro Masrur. 1-6 [doi]
- Towards verifying determinism of SystemC designsHoang M. Le, Rolf Drechsler. 1-4 [doi]
- Energy-efficient scheduling for memory-intensive GPGPU workloadsSeokwoo Song, Minseok Lee, John Kim, Woong Seo, Yeon Gon Cho, Soojung Ryu. 1-6 [doi]
- Compiler-driven dynamic reliability management for on-chip systems under variabilitiesSemeen Rehman, Florian Kriebel, Muhammad Shafique, Jörg Henkel. 1-4 [doi]
- Property directed invariant refinement for program verificationTobias Welp, Andreas Kuehlmann. 1-6 [doi]
- A logic integrated optimal pin-count design for digital microfluidic biochipsTrung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho. 1-6 [doi]
- Signature indexing of design layouts for hotspot detectionCristian Andrades, M. Andrea Rodríguez, Charles C. Chiang. 1-6 [doi]
- Lightweight code-based cryptography: QC-MDPC McEliece encryption on reconfigurable devicesIngo von Maurich, Tim Güneysu. 1-6 [doi]
- Quo vadis, PUF?: Trends and challenges of emerging physical-disorder based securityMasoud Rostami, James Bradley Wendt, Miodrag Potkonjak, Farinaz Koushanfar. 1-6 [doi]
- Implementation issues in the hierarchical composition of performance models of analog circuitsM. Velasco-Jimenez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández. 1-6 [doi]
- Virtual prototype life cycle in automotive applicationsManfred Thanner. 1 [doi]
- Coverage evaluation of post-silicon validation tests with virtual prototypesKai Cong, Li Lei, Zhenkun Yang, Fei Xie. 1-6 [doi]
- Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexingFotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain. 1-6 [doi]
- Leakage-power-aware clock period minimizationHua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh. 1-6 [doi]
- RETLab: A fast design-automation framework for arbitrary RET networksMohammad D. Mottaghi, Arjun Rallapalli, Chris Dwyer. 1-6 [doi]
- Facilitating timing debug by logic path correspondenceOshri Adler, Eli Arbel, Ilia Averbouch, Ilan Beer, Inna Grijnevitch. 1-6 [doi]
- dSVM: Energy-efficient distributed Scratchpad Video Memory Architecture for the next-generation High Efficiency Video CodingFelipe Sampaio, Muhammad Shafique, Bruno Zatt, Sergio Bampi, Jörg Henkel. 1-6 [doi]
- Hardware-based fast exploration of cache hierarchies in application specific MPSoCsIsuru Nawinne, Josef Schneider, Haris Javaid, Sri Parameswaran. 1-6 [doi]
- Chameleon: Channel efficient Optical Network-on-ChipSébastien Le Beux, Hui Li, Ian O'Connor, Kazem Cheshmi, Xuchen Liu, Jelena Trajkovic, Gabriela Nicolescu. 1-6 [doi]
- A dynamic computation method for fast and accurate performance evaluation of multi-core architecturesSebastien Le Nours, Adam Postula, Neil W. Bergmann. 1-6 [doi]
- System design challenges for next generation wireless and embedded systemsDavid Fuller. 1 [doi]
- A cross-level verification methodology for digital IPs augmented with embedded timing monitorsValerio Guarnieri, Massimo Petricca, Alessandro Sassone, Sara Vinco, Nicola Bombieri, Franco Fummi, Enrico Macii, Massimo Poncino. 1-6 [doi]
- Bus designs for time-probabilistic multicore processorsJavier Jalle, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla. 1-6 [doi]
- Advanced SIMD: Extending the reach of contemporary SIMD architecturesMatthias Boettcher, Bashir M. Al-Hashimi, Mbou Eyole, Giacomo Gabrielli, Alastair Reid. 1-4 [doi]
- Low-latency wireless 3D NoCs via randomized shortcut chipsHiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano. 1-6 [doi]
- Unveiling Eurora - Thermal and power characterization of the most energy-efficient supercomputer in the worldAndrea Bartolini, Matteo Cacciari, Carlo Cavazzoni, Giampietro Tecchiolli, Luca Benini. 1-6 [doi]
- An analog non-volatile neural network platform for prototyping RF BIST solutionsDzmitry Maliuk, Yiorgos Makris. 1-6 [doi]
- Metal layer planning for silicon interposers with consideration of routability and manufacturing costWen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang. 1-6 [doi]
- Recovery-based resilient latency-insensitive systemsYuankai Chen, Xuan Zeng, Hai Zhou. 1-6 [doi]
- Dynamic Flip-Flop conversion to tolerate process variation in low power circuitsMehrzad Nejat, Bijan Alizadeh, Ali Afzali-Kusha. 1-4 [doi]
- From Simulink to NoC-based MPSoC on FPGAFrancesco Robino, Johnny Öberg. 1-4 [doi]
- May-happen-in-parallel analysis based on segment graphs for safe ESL modelsWeiwei Chen, Xu Han, Rainer Dömer. 1-6 [doi]
- Utilization-aware load balancing for the energy efficient operation of the big.LITTLE processorMyungsun Kim, Kibeom Kim, James R. Geraci, Seongsoo Hong. 1-4 [doi]
- On GPU bus power reduction with 3D IC technologiesYoung-Joon Lee, Sung Kyu Lim. 1-6 [doi]
- Battery aware stochastic QoS boosting in mobile computing devicesHao Shen, Qiuwen Chen, Qinru Qiu. 1-4 [doi]
- An embedded offset and gain instrument for OpAmp IPsJinbo Wan, Hans G. Kerkhoff. 1-4 [doi]
- Built-in self-test and characterization of polar transmitter parameters in the loop-back modeJae-woong Jeong, Sule Ozev, Shreyas Sen, Vishwanath Natarajan, Mustapha Slamani. 1-6 [doi]
- MSim: A general cycle accurate simulation platform for memcomputing studiesChun Zhang, Peng Deng, Hui Geng, Jianming Liu, Qi Zhu, Jinjun Xiong, Yiyu Shi. 1-5 [doi]
- Predictive parallel event-driven HDL simulation with a new powerful prediction strategySeiyang Yang, Jaehoon Han, Doowhan Kwak, Namdo Kim, Daeseo Cha, Junhyuck Park, Jay Kim. 1-3 [doi]
- Width minimization in the Single-Electron Transistor array synthesisChian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan. 1-4 [doi]
- Automatic specification granularity tuning for design space explorationJiaxing Zhang, Gunar Schirner. 1-6 [doi]
- FEPMA: Fine-grained event-driven power meter for android smartphones based on device driver layer event monitoringKitae Kim, Donghwa Shin, Qing Xie, Yanzhi Wang, Massoud Pedram, Naehyuck Chang. 1-6 [doi]
- Fault-tolerant control synthesis and verification of distributed embedded systemsMatthias Kauer, Damoon Soudbakhsh, Dip Goswami, Samarjit Chakraborty, Anuradha M. Annaswamy. 1-6 [doi]
- Time-decoupled parallel SystemC simulationJan Henrik Weinstock, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Laura Tosoratto. 1-4 [doi]
- Low-voltage organic transistors for flexible electronicsUte Zschieschang, Reinhold Rodel, Ulrike Kraft, Kazuo Takimiya, Tarek Zaki, Florian Letzkus, Joerg Butschke, Harald Richter, Joachim N. Burghartz, Wei Xiong, Boris Murmann, Hagen Klauk. 1-6 [doi]
- Partitioned mixed-criticality scheduling on multiprocessor platformsChuancai Gu, Nan Guan, Qingxu Deng, Wang Yi 0001. 1-6 [doi]
- An adaptive transmitting power technique for energy efficient mm-wave wireless NoCsAndrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania. 1-6 [doi]
- Integrated circuits processing chemical information: Prospects and challengesA. Richter, A. Voigt, René Schüffny, Stephan Henker, M. Volp. 1 [doi]
- Panel: Future SoC verification methodology: UVM evolution or revolution?Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan J. Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev. 1-5 [doi]
- Semi-symbolic analysis of mixed-signal systems including discontinuitiesCarna Radojicic, Christoph Grimm, Javier Moreno, Xiao Pan. 1-4 [doi]
- D2Cyber: A design automation tool for dependable cybercarsArslan Munir, Farinaz Koushanfar. 1-4 [doi]
- Effective resource management towards efficient computingPer Stenström. 1 [doi]
- Contention aware frequency scaling on CMPs with guaranteed quality of serviceHao Shen, Qinru Qiu. 1-6 [doi]
- Statistical static timing analysis using a skew-normal canonical delay modelM. Vijaykumar, V. Vasudevan. 1-6 [doi]
- The connected car and its implication to the automotive chip roadmapMichael Bolle. 1 [doi]
- A low-power, high-performance approximate multiplier with configurable partial error recoveryCong Liu, Jie Han, Fabrizio Lombardi. 1-4 [doi]
- Improving STT-MRAM density through multibit error correctionBrandon Del Bel, Jongyeon Kim, Chris H. Kim, Sachin S. Sapatnekar. 1-6 [doi]
- DARP: Dynamically Adaptable Resilient Pipeline design in microprocessorsHu Chen, Sanghamitra Roy, Koushik Chakraborty. 1-6 [doi]
- Connecting different worlds - Technology abstraction for reliability-aware design and TestUlf Schlichtmann, Veit Kleeberger, Jacob A. Abraham, Adrian Evans, Christina Gimmler-Dumont, Michael Glaß, Andreas Herkersdorf, Sani R. Nassif, Norbert Wehn. 1-8 [doi]
- Organic electronics - From lab to marketsK. Leo. 1 [doi]
- Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baselineLuca Ramini, Alberto Ghiribaldi, Paolo Grani, Sandro Bartolini, Hervé Tatenguem Fankem, Davide Bertozzi. 1-6 [doi]
- Power modeling and analysis in early design phasesBernhard Fischer, Christian Cech, Hannes Muhr. 1-6 [doi]
- Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designsKitae Park, Geunho Kim, Taewhan Kim. 1-4 [doi]
- Hardware primitives for the synthesis of multithreaded elastic systemsGiorgos Dimitrakopoulos, I. Seitanidis, A. Psarras, K. Tsiouris, Pavlos M. Mattheakis, J. Cortadella. 1-4 [doi]
- Extending lifetime of battery-powered coarse-grained reconfigurable computing platformsShouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei. 1-6 [doi]
- Energy-efficient hardware acceleration through computing in the memorySomnath Paul, Robert Karam, Swarup Bhunia, Ruchir Puri. 1-6 [doi]
- ‡Josep Torrellas. 1-5 [doi]
- Efficiency of a glitch detector against electromagnetic fault injectionLoic Zussa, Amine Dehbaoui, Karim Tobich, Jean-Max Dutertre, Philippe Maurine, Ludovic Guillaume-Sage, Jessy Clédière, Assia Tria. 1-6 [doi]
- Make it real: Effective floating-point reasoning via exact arithmeticMiriam Leeser, Saoni Mukherjee, Jaideep Ramachandran, Thomas Wahl. 1-4 [doi]
- Impact of steep-slope transistors on non-von Neumann architectures: CNN case studyIndranil Palit, Behnam Sedighi, Andras Horvath, Xiaobo Sharon Hu, Joseph Nahas, Michael T. Niemier. 1-6 [doi]
- Spintronics for low-power computingYue Zhang, Weisheng Zhao, Jacques-Olivier Klein, Wang Kang, Damien Querlioz, Youguang Zhang, Dafine Ravelosona, Claude Chappert. 1-6 [doi]
- Sensitivity-based weighting for passivity enforcement of linear macromodels in power integrity applicationsA. Ubolli, Stefano Grivet-Talocia, M. Bandinu, Alessandro Chinea. 1-6 [doi]
- Computing a language-based guarantee for timing properties of cyber-physical systemsNeil Dhruva, Pratyush Kumar, Georgia Giannopoulou, Lothar Thiele. 1-6 [doi]
- A universal symmetry detection algorithmPeter M. Maurer. 1-4 [doi]
- Panel: The world is going... analog & mixed-signal! What about EDA?Marco Casale-Rossi, Pietro Palella, Mario Anton, Ori Galzur, Robert Hum, Rainer Kress, Paul Lo. 1-5 [doi]
- ASLAN: Synthesis of approximate sequential circuitsAshish Ranjan, Arnab Raha, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan. 1-6 [doi]
- Panel: Emerging vs. established technologies, a two sphinxes' riddle at the crossroads?Marco Casale-Rossi, Giovanni De Micheli, Rob Aitken, Antun Domic, Manfred Horstmann, Robert Hum, Philippe Magarshack. 1-4 [doi]
- Reliability-aware mapping optimization of multi-core systems with mixed-criticalityShin-Haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele. 1-4 [doi]
- Exploiting narrow-width values for improving non-volatile cache lifetimeGuangshan Duan, Shuai Wang. 1-4 [doi]
- On-device objective-C application optimization framework for high-performance mobile processorsGaro Bournoutian, Alex Orailoglu. 1-6 [doi]
- CoMik: A predictable and cycle-accurately composable real-time microkernelAndrew Nelson, Ashkan Beyranvand Nejad, Anca Mariana Molnos, Martijn Koedam, Kees Goossens. 1-4 [doi]
- Reconfigurable silicon nanowire devices and circuits: Opportunities and challengesWalter M. Weber, Jens Trommer, Matthias Grube, Andre Heinzig, Markus König, Thomas Mikolajick. 1-6 [doi]
- Standard cell library tuning for variability tolerant designsSebastien Fabrie, Juan Diego Echeverri, Maarten Vertregt, José Pineda de Gyvez. 1-6 [doi]
- Bit-Flipping Scan - A unified architecture for fault tolerance and offline testMichael E. Imhof, Hans-Joachim Wunderlich. 1-6 [doi]
- Brain-inspired computing with spin torque devicesKaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra. 1-6 [doi]
- Analysis and evaluation of per-flow delay bound for multiplexing modelsYanchen Long, Zhonghai Lu, Xiaolang Yan. 1-4 [doi]
- A power-efficient reconfigurable architecture using PCM configuration technologyAli Ahari, Hossein Asadi, Behnam Khaleghi, Mehdi Baradaran Tahoori. 1-6 [doi]
- Approximating the age of RF/analog circuits through re-characterization and statistical estimationDoohwang Chang, Sule Ozev, Ozgur Sinanoglu, Ramesh Karri. 1-4 [doi]
- Efficient high-sigma yield analysis for high dimensional problemsMoning Zhang, Zuochang Ye, Yan Wang. 1-6 [doi]
- PUFs at a glanceUlrich Rührmair, Daniel E. Holcomb. 1-6 [doi]
- Process variation-aware workload partitioning algorithms for GPUs supporting spatial-multitaskingPaula Aguilera, Jungseob Lee, Amin Farmahini Farahani, Katherine Morrow, Michael J. Schulte, Nam Sung Kim. 1-6 [doi]
- Improving efficiency of extensible processors by using approximate custom instructionsMehdi Kamal, Amin Ghasemazar, Ali Afzali-Kusha, Massoud Pedram. 1-4 [doi]
- The metamodeling approach to system level synthesisWolfgang Ecker, Michael Velten, Leily Zafari, Ajay Goyal. 1-2 [doi]
- Word-line power supply selector for stability improvement of embedded SRAMs in high reliability applicationsBartomeu Alorda, C. Carmona, Sebastiàn A. Bota. 1-6 [doi]
- Stochastic analysis of Bubble RazorGuowei Zhang, Peter A. Beerel. 1-6 [doi]
- An efficient temperature-gradient based burn-in technique for 3D stacked ICsNima Aghaee, Zebo Peng, Petru Eles. 1-4 [doi]
- An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systemsVito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi. 1-4 [doi]
- IIR filters using stochastic arithmeticNaman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel. 1-6 [doi]
- Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structuresRicardo Martins Abreu e Silva, Nuno C. Lourenço, António Canelas, Nuno Horta. 1-6 [doi]
- The energy benefit of level-crossing sampling including the actuator's energy consumptionBurkhard Hensel, Klaus Kabitzsch. 1-4 [doi]
- Acceptance and random generation of event sequences under real time calculus constraintsKajori Banerjee, Pallab Dasgupta. 1-6 [doi]
- Image progressive acquisition for hardware systemsJianxiong Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung. 1-6 [doi]
- Verification-guided voter minimization in triple-modular redundant circuitsDmitry Burlyaev, Pascal Fradet, Alain Girault. 1-6 [doi]
- Wear-out analysis of Error Correction Techniques in Phase-Change MemoryCaio Hoffman, Luiz Ramos, Rodolfo Azevedo, Guido Araujo. 1-4 [doi]
- Fast STA prediction-based gate-level timing simulationTariq B. Ahmad, Maciej J. Ciesielski. 1-6 [doi]
- Minimizing state-of-health degradation in hybrid electrical energy storage systems with arbitrary source and load profilesYanzhi Wang, Xue Lin, Qing Xie, Naehyuck Chang, Massoud Pedram. 1-4 [doi]
- Modeling steep slope devices: From circuits to architecturesKarthik Swaminathan, Moon Seok Kim, Nandhini Chandramoorthy, Behnam Sedighi, Robert Perricone, Jack Sampson, Vijaykrishnan Narayanan. 1-6 [doi]
- Parallel probe based dynamic connection setup in TDM NoCsShaoteng Liu, Axel Jantsch, Zhonghai Lu. 1-6 [doi]
- Video analytics using beyond CMOS devicesVijaykrishnan Narayanan, Suman Datta, Gert Cauwenberghs, Donald M. Chiarulli, Steven P. Levitan, Philip Wong. 1-5 [doi]
- Impact of resource sharing on performance and performance predictionJan Reineke, Reinhard Wilhelm. 1-2 [doi]
- SSFB: A highly-efficient and scalable simulation reduction technique for SRAM yield analysisManish Rana, Ramon Canal. 1-6 [doi]
- Software architecture of High Efficiency Video Coding for many-core systems with power-efficient workload balancingMuhammad Usman Karim Khan, Muhammad Shafique, Jörg Henkel. 1-6 [doi]
- Concurrent placement, capacity provisioning, and request flow control for a distributed cloud infrastructureShuang Chen, Yanzhi Wang, Massoud Pedram. 1-6 [doi]
- A novel embedded system for vision trackingAntonis Nikitakis, Theofilos Paganos, Ioannis Papaefstathiou. 1-4 [doi]
- Characterizing power delivery systems with on/off-chip voltage regulators for many-core processorsXuan Wang, Jiang Xu, Zhe Wang, Kevin J. Chen, Xiaowen Wu, Zhehui Wang. 1-4 [doi]
- Integrated microfluidic power generation and cooling for bright silicon MPSoCsMohamed M. Sabry, Arvind Sridhar, David Atienza, Patrick Ruch, Bruno Michel. 1-6 [doi]
- EATBit: Effective automated test for binary translation with high code coverageHui Guo, Zhenjiang Wang, Chenggang Wu, Ruining He. 1-6 [doi]
- Advancing CMOS with carbon electronicsFranz Kreupl. 1-6 [doi]
- Partial-SET: Write speedup of PCM main memoryBing Li, Shuchang Shan, Yu Hu, Xiaowei Li 0001. 1-4 [doi]
- Sigma-delta testability for pipeline A/D convertersAntonio J. Ginés, Gildas Leger. 1-6 [doi]
- Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscalesMojtaba Ebrahimi, Adrian Evans, Mehdi Baradaran Tahoori, Razi Seyyedi, Enrico Costenaro, Dan Alexandrescu. 1-6 [doi]
- WCET-Centric dynamic instruction cache lockingHuping Ding, Yun Liang, Tulika Mitra. 1-6 [doi]
- A self-propagating wakeup mechanism for point-to-point networks with partial network supportJan R. Seyler, Thilo Streichert, Juri Warkentin, Matthias Spagele, Michael Glaß, Jürgen Teich. 1-6 [doi]
- A layered approach for testing timing in the model-based implementationBaekGyu Kim, Hyeon I. Hwang, Taejoon Park, Sang Hyuk Son, Insup Lee. 1-4 [doi]
- Hacking and protecting IC hardwareSaid Hamdioui, Jean-Luc Danger, Giorgio Di Natale, Fethulah Smailbegovic, Gerard van Battum, Mark Tehranipoor. 1-7 [doi]
- Interconnect test for 3D stacked memory-on-logicMottaqiallah Taouil, Mahmoud Masadeh, Said Hamdioui, Erik Jan Marinissen. 1-6 [doi]
- Simple interpolants for linear arithmeticChristoph Scholl, Florian Pigorsch, Stefan Disch, Ernst Althaus. 1-6 [doi]
- Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chipAmmar Karkar, Nizar Dahir, Ra'ed Al-Dujaily, Kenneth Tong, Terrence S. T. Mak, Alex Yakovlev. 1-4 [doi]
- The growing importance of microelectronics from a foundry perspectiveGerd Teepe. 1 [doi]
- Mission profile aware IC design - A case studyGoeran Jerke, Andrew B. Kahng. 1-6 [doi]
- Temporal memoization for energy-efficient timing error recovery in GPGPUsAbbas Rahimi, Luca Benini, Rajesh K. Gupta. 1-6 [doi]
- A Linux-governor based Dynamic Reliability Manager for android mobile devicesPietro Mercati, Andrea Bartolini, Francesco Paterna, Tajana Simunic Rosing, Luca Benini. 1-4 [doi]
- Rewiring for threshold logic circuit minimizationChia-Chun Lin, Chun-Yao Wang, Yung-Chih Chen, Ching-Yi Huang. 1-6 [doi]
- Time-critical computing on a single-chip massively parallel processorBenoît Dupont de Dinechin, Duco van Amstel, Marc Poulhiès, Guillaume Lager. 1-6 [doi]
- Equivalence checking for function pipelining in behavioral synthesisKecheng Hao, Sandip Ray, Fei Xie. 1-6 [doi]
- A minimalist approach to Remote AttestationAurélien Francillon, Quan Nguyen, Kasper Bonne Rasmussen, Gene Tsudik. 1-6 [doi]
- Design of safety critical systems by refinementAlex Iliasov, Arseniy Alekseyev, Danil Sokolov, Andrey Mokhov. 1-4 [doi]
- P/G TSV planning for IR-drop reduction in 3D-ICsShengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi Baradaran Tahoori. 1-6 [doi]
- Special session: How secure are PUFs really? On the reach and limits of recent PUF attacksUlrich Rührmair, Ulf Schlichtmann, Wayne Burleson. 1-4 [doi]
- Novel circuit topology synthesis method using circuit feature mining and symbolic comparisonCristian Ferent, Alex Doboli. 1-4 [doi]
- Transient errors resiliency analysis technique for automotive safety critical applicationsSujan Pandey, Bart Vermeulen. 1-4 [doi]
- Resistive memories: Which applications?Fabien Clermidy, Natalija Jovanovic, Santhosh Onkaraiah, Houcine Oucheikh, Olivier Thomas, Ogun Turkyilmaz, Elisa Vianello, Jean Michel Portal, Marc Bocquet. 1-6 [doi]
- Optimization of design complexity in time-multiplexed constant multiplicationsLevent Aksoy, Paulo F. Flores, José C. Monteiro. 1-4 [doi]
- Highly accurate SPICE-compatible modeling for single- and double-gate GNRFETs with studies on technology scalingMorteza Gholipour, Ying-Yu Chen, Amit Sangai, Deming Chen. 1-6 [doi]
- Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAMRajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori. 1-6 [doi]
- VRCon: Dynamic reconfiguration of voltage regulators in a multicore platformWoojoo Lee, Yanzhi Wang, Massoud Pedram. 1-6 [doi]
- Moving from co-simulation to simulation for effective smart systems designFranco Fummi, Michele Lora, Francesco Stefanni, Dimitrios Trachanis, Jahn Vanhese, Sara Vinco. 1-4 [doi]
- A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/OsSih-Sian Wu, Kanwen Wang, Sai Manoj Pudukotai Dinakarrao, Tsung-Yi Ho, Mingbin Yu, Hao Yu. 1-4 [doi]
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- Accelerating graph computation with racetrack memory and pointer-assisted graph representationEunhyuk Park, Sungjoo Yoo, Sunggu Lee, Helen Li. 1-4 [doi]
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- Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clustersPaolo Burgio, Giuseppe Tagliavini, Francesco Conti, Andrea Marongiu, Luca Benini. 1-6 [doi]
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- A hybrid non-volatile SRAM cell with concurrent SEU detection and correctionPilin Junsangsri, Fabrizio Lombardi, Jie Han. 1-4 [doi]
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- Resource optimization for CSDF-modeled streaming applications with latency constraintsDi Liu, Jelena Spasic, Jiali Teddy Zhai, Todor Stefanov, Gang Chen. 1-6 [doi]
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- Probabilistic standard cell modeling considering non-Gaussian parameters and correlationsAndré Lange, Christoph Sohrmann, Roland Jancke, Joachim Haase, Ingolf Lorenz, Ulf Schlichtmann. 1-4 [doi]
- Rate-adaptive tasks: Model, analysis, and design issuesGiorgio C. Buttazzo, Enrico Bini, Darren Buttle. 1-6 [doi]
- Monitoring and WCET analysis in COTS multi-core-SoC-based mixed-criticality systemsJan Nowotsch, Michael Paulitsch, Arne Henrichsen, Werner Pongratz, Andreas Schacht. 1-5 [doi]
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- Effective post-silicon failure localization using dynamic program slicingOphir Friedler, Wisam Kadry, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin. 1-6 [doi]
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- An energy-aware fault tolerant scheduling framework for soft error resilient cloud computing systemsYue Gao, Sandeep K. Gupta, Yanzhi Wang, Massoud Pedram. 1-6 [doi]
- Yield and timing constrained spare TSV assignment for three-dimensional integrated circuitsYu-Guang Chen, Kuan-Yu Lai, Ming-Chao Lee, Yiyu Shi, Wing-Kai Hon, Shih-Chieh Chang. 1-4 [doi]
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- Hardware/software approach for code synchronization in low-power multi-core sensor nodesRuben Braojos, Ahmed Yasir Dogan, Ivan Beretta, Giovanni Ansaloni, David Atienza. 1-6 [doi]
- Model-based protocol log generation for testing a telecommunication test harness using CLPKenneth Balck, Olga Grinchtein, Justin Pearson. 1-4 [doi]
- Coarse-grained Bubble Razor to exploit the potential of two-phase transparent latch designsHayoung Kim, Dongyoung Kim, Jae-Joon Kim, Sungjoo Yoo, Sunggu Lee. 1-6 [doi]
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- An efficient manipulation package for Biconditional Binary Decision DiagramsLuca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 1-6 [doi]
- Optimization of standard cell based detailed placement for 16 nm FinFET processYuelin Du, Martin D. F. Wong. 1-6 [doi]
- Optimized buffer allocation in multicore platformsMaximilian Odendahl, Andres Goens, Rainer Leupers, Gerd Ascheid, Benjamin Ries, Berthold Vöcking, Tomas Henriksson. 1-6 [doi]
- Application mapping for express channel-based networks-on-chipDi Zhu, Lizhong Chen, Siyu Yue, Massoud Pedram. 1-6 [doi]
- A low-cost radiation hardened flip-flopYang Lin, Mark Zwolinski, Basel Halak. 1-6 [doi]
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- Distributed cooperative shared last-level caching in tiled multiprocessor system on chipPreethi P. Damodaran, Stefan Wallentowitz, Andreas Herkersdorf. 1-4 [doi]
- p-OFTL: An object-based semantic-aware parallel flash translation layerWei Wang, Youyou Lu, Jiwu Shu. 1-6 [doi]
- Partial witnesses from preprocessed quantified Boolean formulasMartina Seidl, Robert Könighofer. 1-6 [doi]
- Minimally buffered single-cycle deflection routerGnaneswara Rao Jonna, John Jose, Rachana Radhakrishnan, Madhu Mutyam. 1-4 [doi]
- Real-time optimization of the battery banks lifetime in Hybrid Residential Electrical SystemsMaurizio Rossi, Alessandro Toppano, Davide Brunelli. 1-6 [doi]
- HEROIC: Homomorphically EncRypted One Instruction ComputerNektarios Georgios Tsoutsos, Michail Maniatakos. 1-6 [doi]
- A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clustersPaolo Burgio, Robin Danilo, Andrea Marongiu, Philippe Coussy, Luca Benini. 1-4 [doi]
- Automated system testing using dynamic and resource restricted clientsMirko Caspar, Mirko Lippmann, Wolfram Hardt. 1-4 [doi]
- Memcomputing: The cape of good hope: [Extended special session description]Yiyu Shi, Hung-Ming Chen. 1-3 [doi]
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- Thinfilm printed ferro-electric memories and integrated productsChrister Karlsson, Peter Fischer. 1 [doi]
- Nostradamus: Low-cost hardware-only error detection for processor coresRalph Nathan, Daniel J. Sorin. 1-6 [doi]
- Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacksBao Liu, Brandon Wang. 1-6 [doi]
- Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit designAdarsh Reddy Ashammagari, Hamid Mahmoodi, Houman Homayoun. 1-6 [doi]
- Dynamic construction of circuits for reactive traffic in homogeneous CMPsMarta Ortín, Darío Suárez Gracia, Maria Villarroya, Cruz Izu, Víctor Viñals. 1-4 [doi]
- SKETCHILOG: Sketching combinational circuitsAndrew Becker, David Novo, Paolo Ienne. 1-4 [doi]
- SAFE: Security-Aware FlexRay Scheduling EngineGang Han, Haibo Zeng, Yaping Li, Wenhua Dou. 1-4 [doi]
- Failure analysis of a network-on-chip for real-time mixed-critical systemsEberle A. Rambo, Alexander Tschiene, Jonas Diemer, Leonie Ahrendts, Rolf Ernst. 1-4 [doi]
- Energy efficient data flow transformation for Givens Rotation based QR DecompositionNamita Sharma, Preeti Ranjan Panda, Min Li, Prashant Agrawal, Francky Catthoor. 1-4 [doi]
- Modeling and analysis of digital linear dropout regulators with adaptive control for high efficiency under wide dynamic range digital loadsSamantak Gangopadhyay, Youngtak Lee, Saad Bin Nasir, Arijit Raychowdhury. 1-6 [doi]
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- Multi-objective distributed run-time resource management for many-coresStefan Wildermann, Michael Glaß, Jürgen Teich. 1-6 [doi]
- ArChiVED: Architectural checking via event digests for high performance validationChang-Hong Hsu, Debapriya Chatterjee, Ronny Morad, Raviv Gal, Valeria Bertacco. 1-6 [doi]
- hevcDTM: Application-driven Dynamic Thermal Management for High Efficiency Video CodingDaniel Palomino, Muhammad Shafique, Hussam Amrouch, Altamiro Amadeu Susin, Jörg Henkel. 1-4 [doi]
- Model-based actor multiplexing with application to complex communication protocolsChristian Zebelein, Christian Haubelt, Joachim Falk, Tobias Schwarzer, Jürgen Teich. 1-4 [doi]
- Software-based Pauli tracking in fault-tolerant quantum circuitsAlexandru Paler, Simon Devitt, Kae Nemoto, Ilia Polian. 1-4 [doi]
- ALLARM: Optimizing sparse directories for thread-local dataAmitabha Roy, Timothy M. Jones. 1-6 [doi]
- Multi-disciplinary integrated design automation tool for automotive cyber-physical systemsArquimedes Canedo, Mohammad Abdullah Al Faruque, Jan H. Richter. 1-2 [doi]
- A low power and robust carbon nanotube 6T SRAM design with metallic toleranceLuo Sun, Jimson Mathew, Rishad A. Shafik, Dhiraj K. Pradhan, Zhen Li. 1-4 [doi]
- A tree arbiter cell for high speed resource sharing in asynchronous environmentsSyed Rameez Naqvi, Andreas Steininger. 1-6 [doi]
- Global fan speed control considering non-ideal temperature measurements in enterprise serversJungsoo Kim, Mohamed M. Sabry, David Atienza, Kalyan Vaidyanathan, Kenny Gross. 1-6 [doi]
- Joint communication scheduling and interconnect synthesis for FPGA-based many-core systemsAlessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo. 1-4 [doi]
- Provably minimal energy using coordinated DVS and power gatingNathaniel A. Conos, Saro Meguerdichian, Foad Dabiri, Miodrag Potkonjak. 1-6 [doi]
- Multi-variant-based design space exploration for automotive embedded systemsSebastian Graf, Michael Glaß, Jürgen Teich, Christoph Lauer. 1-6 [doi]
- Hardware implementation of a Reed-Solomon soft decoder based on information set decodingStefan Scholl, Norbert Wehn. 1-6 [doi]
- Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chipFrancesco Beneventi, Andrea Bartolini, Pascal Vivet, Denis Dutoit, Luca Benini. 1-4 [doi]
- Attack-resilient sensor fusionRadoslav Ivanov, Miroslav Pajic, Insup Lee. 1-6 [doi]
- EDA tools trust evaluation through security property proofsYier Jin. 1-4 [doi]
- Thermal management of batteries using a hybrid supercapacitor architectureDonghwa Shin, Massimo Poncino, Enrico Macii. 1-6 [doi]
- Context aware power management for motion-sensing body area network nodesFilippo Casamassima, Elisabetta Farella, Luca Benini. 1-6 [doi]
- Functional test generation guided by steady-state probabilities of abstract designJian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li 0001. 1-4 [doi]
- Early design stage thermal evaluation and mitigation: The locomotiv architectural caseTanguy Sassolas, Chiara Sandionigi, Alexandre Guerre, Alexandre Aminot, Pascal Vivet, Hela Boussetta, Luca Ferro, Nicolas Peltier. 1-2 [doi]
- Sub-threshold logic circuit design using feedback equalizationMahmoud Zangeneh, Ajay Joshi. 1-6 [doi]
- ABACUS: A technique for automated behavioral synthesis of approximate computing circuitsKumud Nepal, Yueting Li, R. Iris Bahar, Sherief Reda. 1-6 [doi]
- Formal verification of taint-propagation security properties in a commercial SoC designPramod Subramanyan, Divya Arora. 1-2 [doi]
- Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMsMeng-Ling Tsai, Yi-Jung Chen, Yi-Ting Chen, Ru-Hua Chang. 1-6 [doi]
- Technology transfer towards Horizon 2020Rainer Leupers, Norbert When, Rainer Leupers, Marco Roodzant, Johannes Stahl, Luca Fanucci, Albert Cohen, Bernd Janson. 1 [doi]
- Asynchronous design for new on-chip wide dynamic range power electronicsDelong Shang, Xuefu Zhang, Fei Xia, Alex Yakovlev. 1-6 [doi]
- Testing PUF-based secure key storage circuitsMafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale. 1-6 [doi]
- Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPsHong Chinh Doan, Haris Javaid, Sri Parameswaran. 1-6 [doi]
- Energy optimization in Android applications through wakelock placementFaisal Alam, Preeti Ranjan Panda, Nikhil Tripathi, Namita Sharma, Sanjiv Narayan. 1-4 [doi]
- Trade-offs in execution signature compression for reliable processor systemsJonah Caplan, Maria Isabel Mera, Peter Milder, Brett H. Meyer. 1-6 [doi]
- Implicit index-aware model order reduction for RLC/RC networksNicodemus Banagaaya, Giuseppe Alì, Wil H. A. Schilders, Caren Tischendorf. 1-6 [doi]