A high performance SEU-tolerant latch for nanoscale CMOS technology

Zhengfeng Huang. A high performance SEU-tolerant latch for nanoscale CMOS technology. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014. pages 1-5, IEEE, 2014. [doi]

Abstract

Abstract is missing.