Andy Heinig - researchr alias

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Viewing Publication 1 - 15 from 15

2020

13-Gb/s Transmitter for Bunch of Wires Chip-to-Chip Interface StandardMuhammad Waqas Chaudhary, Andy Heinig, Bhaskar Choubey. mwscas 2020: 333-336 [doi]

Interconnect Aware Power Optimization of Low Swing Driver for Multi-Chip InterfacesMuhammad Waqas Chaudhary, Andy Heinig, Bhaskar Choubey. icecsys 2020: 1-4 [doi]

2019

Fraunhofer's Initial and Ongoing Contributions in 3D IC IntegrationPeter Ramm, Armin Klumpp, Christof Landesberger, Josef Weber, Andy Heinig, Peter Schneider, Günter Elst, Manfred Engelhardt. 3dic 2019: 1-5 [doi]

2016

Interposer based integration to achieve high speed interfaces for ADC applicationMuhammad Waqas Chaudhary, Andy Heinig, Michael Dittrich. 3dic 2016: 1-4 [doi]

Co-design of CML IO and Interposer channel for low area and power signalingMuhammad Waqas Chaudhary, Andy Heinig. ddecs 2016: 84-89 [doi]

2015

Enabling automatic system design optimization through Assembly Design KitsAndy Heinig, Robert Fischbach. 3dic 2015: [doi]

Current and future 3D activities at FraunhoferAndy Heinig, Muhammad Waqas Chaudhary, Peter Schneider, Peter Ramm, Josef Weber. 3dic 2015: [doi]

2014

2013

Layout dependent synthesis for manufacturing costs optimized 3D integrated systemsAndy Heinig. 3dic 2013: 1-6 [doi]

XML-Based Hierarchical Description of 3D Systems and SIPSusann Wolf, Andy Heinig, Uwe Knöchel. dt, 30(3):59-69, 2013. [doi]

2011

Multi-step approach for thermal optimization of 3D-IC and packageAndy Heinig, Christoph Sohrmann. 3dic 2012: 1-5 [doi]

2010

Integration of multi physics modeling of 3D stacks into modern 3D data structuresPeter Schneider, Andy Heinig, Robert Fischbach, Jens Lienig, Sven Reitz, Jörn Stolle, Andreas Wilde. 3dic 2010: 1-6 [doi]

2006

Zeitbeschränkte Clusterung zur Design-Space-Exploration geclusterter VLIW-ProzessorenAndy Heinig, Mario Schölzel. mbmv 2006: 319-328

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