Abstract is missing.
- Characterization of Low-Height Solder Microbump Bonding for Fine-Pitch Inter-Chip Connection in 3DICsYuki Miwa, Sungho Lee, Rui Liang, Kousei Kumahara, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka. 1-4 [doi]
- Die to Wafer Direct Hybid Bonding Demonstration with High Alignment Accuracy and Electrical YieldsAmadine Jouve, L. Sanchez, C. Castan, N. Bresson, F. Fournel, N. Raynaud, P. Metzger. 1-7 [doi]
- High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the Bumpless TSV TechnologyKoji Sakui, Takayuki Ohba. 1-4 [doi]
- Investigation of the Underfill with Negative-Thermal-Expansion Material to Suppress Mechanical Stress in 3D Integration SystemHisashi Kino, Takafumi Fukushima, Tetsu Tanaka. 1-4 [doi]
- An Accurate Assessment of Chip-Package Interaction is a Key Factor for Designing Resilient 3D IC SystemsValeriy Sukharev, Armen Kteyan, Jun-Ho Choy. 1-6 [doi]
- Vertical Optical and Electrical Interconnection for Chip-Scale-Packaged Si Photonic TransceiversKoichi Takemura, Akio Ukita, Yasuhiro Ibusuki, Mitsuru Kurihara, Akihiro Noriki, Takeru Amano, Daisuke Okamoto, Yasuyuki Suzuki, Kazuhiko Kurata. 1-6 [doi]
- Development of Laser-Assisted Bonding with Compression (LABC) Process for 3D IC IntegrationKwang-Seong Choi, Yong-Sung Eom, Seok Hwan Moon, Jiho Joo, Kwangjoo Lee, Jung Hak Kim, Ju Hyeon Kim. 1-3 [doi]
- Investigation of the Influence of Material Properties on Warpage and Solder Joint Reliability of 2.5D & FO PackageKoji Hamaguchi, Mitsuki Nakata, Kouta Segawa, Naoya Suzuki, Toshihisa Nonaka. 1-6 [doi]
- X-ray Photon-Counting Imager with CdTe/Si-LSI StackingToru Aoki, Katsuyuki Takagi, Toshiyuki Takagi, Hiroki Kase, Akifumi Koike. 1-4 [doi]
- Temperature Cycling Reliability of WOW Bumpless Through Silicon ViasChia-Hsuan Lee, Hsin-Chi Chang, Jui-Han Liu, Hiroyuki Ito, Young-Suk Kim, Kuan-Neng Chen, Takayuki Ohba. 1-4 [doi]
- Cu Diffusion Barrier Properties of Various CoWB Electroless Plated Films on SiO2/Si Substrate for Via-last TSV ApplicationT. Matsudaira, S. Shindo, T. Shimizu, T. Ito, S. Shinguhara, S. Shimizu. 1-4 [doi]
- Multichip CMOS Image Sensor Structure for Flash Image AcquisitionYoshiaki Hagiwara. 1-6 [doi]
- Hydrolysis-Tolerant Hybrid Bonding in Ambient Atmosphere for 3D IntegrationAkitsu Shigetou, Tilo H. Yang, C. Robert Kao. 1-3 [doi]
- Power-Performance Advantages of InFO Technology for Advanced System IntegrationChuei-Tang Wang, Douglas Yu. 1-4 [doi]
- Study of Optimizing Stress-Strain Curve of Adhesive for High Expansion TapeTadatomo Yamada, Ken Takano, Toshiaki Menjo, Shinya Takyu. 1-4 [doi]
- Design and Evaluation of a Novel and Ultra-Compact Fully-TGV-based Self-Shielding Bandpass Filter for 5G ApplicationsZiyue Zhang, Yingtao Ding, Zhiming Chen, Mingrui Zhou, Lei Xiao, Ziru Cai, Miao Xiong, Xiao Gong. 1-4 [doi]
- Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and LimitationsOlivier Billoint, Karim Azizi-Mourier, Gerald Cibrario, Didier Lattard, M. Mouhdach, Sebastien Thuries, Pascal Vivet. 1-5 [doi]
- Design Considerations and Fabrication Challenges of Surface Electrode Ion Trap with TSV IntegrationJing Tao, HongYu Li, Peng Zhao, Yu Dian Lim, Anak Agung Alit Apriyana, Chuan Seng Tan. 1-5 [doi]
- TiN Guard Ring Around TSV for Cross-Talk Suppression of Parallel Networking of Data CenterAlit Apriyana Anak Agung, Peng Zhao, Chuan Seng Tan. 1-4 [doi]
- Process Complexity and Cost Considerations of Multi-Layer Die StacksDimitrios Velenis, Joeri De Vos, Soon-Wook Kim, Jaber Derakhshandeh, Pieter Bex, Giovanni Capuz, Samuel Suhard, Kenneth June Rebibis, Stefaan Van Huylenbroeck, Erik Jan Marinissen, Alain Phommahaxay, Andy Miller, Gerald Beyer, Geert Van der Plas, Eric Beyne. 1-6 [doi]
- Hierarchical Design Methodology and Optimization for Proximity Communication based Contactless 3D ThruChip InterfaceSrinivasan Gopal, Deukhyoun Heo, Tanay Karnik. 1-6 [doi]
- Growth Optimization of Multi-Layer Graphene for Thermal-TSV Application in 3D-LSIMariappan Murugesan, Mitsumasa Koyanagi, Takafumi Fukushima. 1-5 [doi]
- Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-IntegrationMariappan Murugesan, Mitsumasa Koyanagi, Hiroyuki Hashimoto, Ji Chel Bea, Takafumi Fukushima. 1-4 [doi]
- Transformer-Less Floating Gate Driver for 3D Power SoCMinami Nakayama, Seiya Abe, Satoshi Matsumoto. 1-4 [doi]
- 3D Test Wrapper Chain Optimization with I/O Cells Binding ConsideredFan-Hsuan Tang, Hsu-Yu Kao, Shih-Hsu Huang, Jin-Fu Li. 1-4 [doi]
- Cu-Cu Bonding Challenges with 'i-ACF' for Advanced 3D IntegrationShunji Kurooka, Yoshinori Hotta, Ai Nakamura, Mitsumasa Koyanagi, Takafumi Fukushima. 1-4 [doi]
- Investigation of Low Temperature Cu Pillar Eutectic Bonding for 3D Chip Stacking TechnologyYi-Chieh Tsai, Chia-Hsuan Lee, Kuan-Neng Chen. 1-4 [doi]
- 3D Integration Technologies for the Stacked CMOS Image SensorsY. Kagawa, H. Iwamoto. 1-4 [doi]
- Variability Cancellation to Improve Diagnostic Performance of Testing through Silicon Vias in Power Distribution Network of 3D-ICKoutaro Hachiya, Atsushi Kurokawa. 1-6 [doi]
- A Graph-Based Model of Micro-Transfer Printing for Cost-Optimized Heterogeneous 2.5D SystemsRobert Fischbach, Tilman Horst, Jens Lienig. 1-6 [doi]
- Towards a Complete Direct Hybrid Bonding D2W Integration Flow: Known-Good-Dies and Die Planarization Modules DevelopmentE. Bourjot, P. Stewart, C. Dubarry, E. Lagoutte, E. Rolland, N. Bresson, G. Romano, D. Scevola, V. Balan, Jérôme Dechamp, Marc Zussy, G. Mauguen, C. Castan, L. Sanchez, Amadine Jouve, F. Fournel, Séverine Cheramy. 1-5 [doi]
- Heterogeneous and 3D Integration at DARPATimothy M. Hancock, Jeffrey C. Demmin. 1-4 [doi]
- Fraunhofer's Initial and Ongoing Contributions in 3D IC IntegrationPeter Ramm, Armin Klumpp, Christof Landesberger, Josef Weber, Andy Heinig, Peter Schneider, Günter Elst, Manfred Engelhardt. 1-5 [doi]
- Electrostatic Shield TSVs to Suppress Coupling Among Stacked ICsYuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi. 1-3 [doi]
- Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder CoreWei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi. 1-4 [doi]
- Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO2 for Low-Temperature TSV Liner FormationRui Liang, Sungho Lee, Yuki Miwa, Kousei Kumahara, Mariappan Murugesan, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka. 1-4 [doi]
- Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI WafersMasahide Goto, Joeri De Vos, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Eiji Higurashi, Yuki Honda, Takuya Saraya, Masaharu Kobayashi, Hiroshi Toshiyoshi, Toshiro Hiramoto. 1-4 [doi]
- Fabrication of High Quality InAs-on-Lnsulator Structures by Smart Cut Process with Reuse of InAs WafersKei Sumita, Jun Takeyasu, Kimihiko Kato, Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi. 1-2 [doi]
- Study of MacEtch using Additives for Preparation of TSVShunsuke Hanatani, Takuya Yorioka, Tomohiro Shimizu, Takeshi Ito, Shoso Shingubara. 1-4 [doi]
- Photoelectroscopic Study of Mn Barrier Layer on SiO2 for Si Wafer Bonding ProcessTakahiro Nagata, Kazumichi Tsumura, Kenro Nakamura, Kengo Uchida, Jin Kawakita, Toyohiro Chikyow, Kazuyuki Higashi. 1-4 [doi]
- Stacked Pixel Sensor/Detector Technology using Au Micro-Bump JunctionMakoto Motoyoshi, Kohki Yanagimura, Taikoh Fushimi, Shunta Endo. 1-4 [doi]
- Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & RouteGiuliano Sisto, Peter Debacker, Rongmei Chen, Geert Van der Plas, Richard Chou, Eric Beyne, Dragomir Milojevic. 1-4 [doi]
- A Universal ADC for Sensor ApplicationsAkira Matsuzawa. 1-4 [doi]
- Development of a CDS Circuit for 3-D Stacked Neural Network Chip using CMOS Analog Signal ProcessingKoji Kiyoyama, Qian Zhengy, Hiroyuki Hashimoto, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka. 1-4 [doi]
- Protective Layer for Collective Die to Wafer Hybrid BondingFumihiro Inoue, Julien Bertheau, Samuel Suhard, Alain Phommahaxay, Takuya Ohashi, Tetsuro Kinoshita, Yohei Kinoshita, Eric Beyne. 1-4 [doi]
- Development of 3D-IC Embedded Flexible Hybrid SystemSungho Lee, Yuki Susumago, Zhengyang Qian, Noriyuki Takahashi, Hisashi Kino, Tetsu Tanaka, Takafumi Fukushima. 1-4 [doi]
- A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICsWei-Hsuan Yang, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun, Shih-Hsu Huang. 1-3 [doi]
- An Introduction to Marching Memory (MM)Tadao Nakamura. 1-3 [doi]
- Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICsTakuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi. 1-4 [doi]
- A 6.9 μm Pixel-Pitch 3D Stacked Global Shutter CMOS Image Sensor with 3M Cu-Cu connectionsTsukasa Miura, Masaki Sakakibara, Hirotsugu Takahashi, Tadayuki Taura, Keiji Tatani, Yusuke Oike, Takayuki Ezaki. 1-2 [doi]
- Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnectsImed Jani, Didier Lattard, Pascal Vivet, Lucile Arnaud, Edith Beigné. 1-4 [doi]
- SiN used as a Stressor in Germanium-On-Insulator SubstrateSethavut Duangchan, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Akiyoshi Baba. 1-5 [doi]
- On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC InterconnectionToshiaki Satoh, Hiroyuki Yotsuyanagi, Masaki Hashizume. 1-4 [doi]
- Effects of Argon and Nitrogen ion Bombardments on Sputtered and Electroplated Cu Surfaces for Cu Bonding ApplicationHan Kyeol Seo, Hae-Sung Park, Sarah Eunkyung Kim. 1-4 [doi]
- Heat Transfer in Nanostructured Si and Heat Flux Control TechniqueMasahiro Nomura. 1-4 [doi]
- Low Temperature Cu to Cu Direct Bonding below 150 °C with Au Passivation LayerDemin Liu, Po-Chih Chen, Yi-Chieh Tsai, Kuan-Neng Chen. 1-4 [doi]
- Vertical Stack Thermal Characterization of Heterogeneous Integration and PackagesT. Robert Harris, W. Rhett Davis, Steven Lipa, W. Shepherd Pitts, Paul D. Franzon. 1-3 [doi]
- 3D Integrated Pixel Sensor with Silicon-on-Insulator Technology for the International Linear Collider ExperimentMiho Yamada, Shun Ono, Yasuo Arai, Ikuo Kurachi, Toru Tsuboyama, Masayuki Ikebe, Makoto Motoyoshi. 1-4 [doi]
- Low-Temperature Wafer-Level Metal Bonding with Gold Thin Film at 100 °CPo-Chih Chen, Demin Liu, Kuan-Neng Chen. 1-4 [doi]
- Thermal Stress Tracking in Multi-Die 3D Stacking Structure by Finite Element AnalysisCheong-Ha Jung, Won Seo, Gu-sung Kim. 1-2 [doi]
- A Design Scheme for 3-D Stacked CNN AcceleratorsJubee Tada, Kazuto Takahashi, Ryusuke Egawa. 1-4 [doi]
- Characterization of Nitride Passivated Cu Surface for Low-Temperature Cu-Cu BondingHae-Sung Park, Han Kyeol Seo, Sarah Eunkyung Kim. 1-4 [doi]
- Reduction of TSV PumpingQuy Dinh, Kazuo Kondo, Tetsuji Hirato. 1-4 [doi]
- Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded DiodesHanna Soneda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu. 1-5 [doi]
- High Density and Low-Temperature Interconnection Enabled by Mechanical Self-Alignment and Electroless PlatingSreejith Kochupurackal Rajan, Ming Jui Li, Muhannad S. Bakir, Gary S. May. 1-4 [doi]
- Crystallinity Dependence of Long-Term Reliability of Electroplated Gold Thin-Film InterconnectionsKen Suzuki, Ryota Mizuno, Yutaro Nakoshi, Hideo Miura. 1-5 [doi]
- Optical TSV Using Si-Photonics Integrated Curved Micro-MirrorAkihiro Noriki, Isao Tamai, Yasuhiro Ibusuki, Akio Ukita, Satoshi Suda, Daisuke Shimura, Yosuke Onawa, Hiroki Yaegashi, Takeru Amano. 1-4 [doi]
- Collective and Gang Bonding for Three-Dimensional Integrated Circuits in Chip-on-Wafer ProcessHiroto Tanaka, Yoshiyuki Arai, Toshiyuki Jinda, Noboru Asahi, Katsumi Terada. 1-3 [doi]