Abstract is missing.
- A holistic view of chip-level thermal architecture from heterogeneous stacked dice to system level in telecoms applicationsGamal Refai-Ahmed, Ivor Barber, Anthony Torza, Brian Philofsky. [doi]
- New signal skew cancellation method for 2 Gbps transmission in glass and organic interposers to achieve 2.5D package employing next generation high bandwidth memory (HBM)Shuuichi Kariyazaki, Kenichi Kuboyama, Ryuichi Oikawa, Takuo Funaya. [doi]
- Noise coupling modeling and analysis of through glass via(TGV)Insu Hwang, Jihye Kim, YoungWoo Kim, Jonghyun Cho, Joungho Kim. [doi]
- An ultra-fast temporary bonding and release process based on thin photolysis polymer in 3D integrationTsung-Yen Tsai, Chien-Hung Lin, Chia-Lin Lee, Shan-Chun Yang, Kuan-Neng Chen. [doi]
- Advanced 2.5D/3D hetero-integration technologies at GINTI, Tohoku UniversityK. W. Lee, Ji Chel Bea, Mitsu Koyanagi, Takafumi Fukushima, Tetsu Tanaka. [doi]
- IME's capabilities and programs in 2.5D/3DICVempati Srinivasa Rao. [doi]
- On TSV array defect detection method using two ring-oscillators considering signal transitions at adjacent TSVsHiroyuki Yotsuyanagi, Akihiro Fujiwara, Masaki Hashizume. [doi]
- Power tile optimization and packaging for efficient temperature management of ASIC's in networking applicationsSusheela Narasimhan. [doi]
- 3D research activities in ITRIWei-Chung Lo. [doi]
- Invited talk: Progress in 3D integrated circuitsRobert Patti. [doi]
- Computing in 3DPaul D. Franzon, Eric Rotenberg, W. Rhett Davis, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Marcus Tshibangu, Steve Lipa. [doi]
- Electrical interconnect test method of 3D ICs by injected charge volumeDaisuke Suga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu. [doi]
- Fine-grained 3-D integrated circuit fabric using vertical nanowiresMostafizur Rahman, Santosh Khasanvis, Jiajun Shi, Mingyu Li, Csaba Andras Moritz. [doi]
- Thermal stability of electroplated copper thin-film interconnectionsPornvitoo Rittinon, Ken Suzuki, Hideo Miura. [doi]
- Electrical performance of high bandwidth memory (HBM) interposer channel in terabyte/s bandwidth graphics moduleHyunsuk Lee, Kyungjun Cho, Heegon Kim, Sumin Choi, Jaemin Lim, Joungho Kim. [doi]
- 3D advanced integration technology for heterogeneous systemsPascal Vivet, Christian Bernard, Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, G. Pillonnet, Yvain Thonnart, Arnaud Garnier, Didier Lattard, Amandine Jouve, Franck Bana, Thierry Mourier, Séverine Cheramy. [doi]
- Variation of thermal stress in TSV structures caused by crystallinity of electroplated copper interconnectionsJiatong Liu, Ken Suzuki, Hideo Miura. [doi]
- Nano-Function materials for TSV technologiesHiroaki Ikeda, Shigenobu Sekine, Ryuji Kimura, Koichi Shimokawa, Keiji Okada, Hiroaki Shindo, Tatsuya Ooi, Rei Tamaki, Makoto Nagata. [doi]
- All-wet TSV filling with highly adhesive displacement plated Cu seed layerKohei Ohta, Atsushi Hirate, Yuto Miyachi, Tomohiro Shimizu, Shoso Shingubara. [doi]
- Invited talk: Technology and overview of Sony's 3D stacked CMOS image sensorTomoharu Ogita. [doi]
- Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitorsSeiya Tanikawa, Hisashi Kino, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka. [doi]
- Long term efficacy of ultra-thin Ti passivation layer for achieving low temperature, low pressure Cu-Cu Wafer-on-Wafer bondingAsisa Kumar Panigrahi, Satish Bonam, Tamal Ghosh, Siva Rama Krishna Vanjari, Shiv Govind Singh. [doi]
- Intermediate BEOL process influence on power and performance for 3DVLSIHossam Sarhan, Sebastien Thuries, Olivier Billoint, Fabien Deprat, Alexandre Ayres De Sousa, Perrine Batude, Claire Fenouillet-Béranger, Fabien Clermidy. [doi]
- Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bondingTakafumi Fukushima, Taku Suzuki, Hideto Hashiguchi, Chisato Nagai, Jichoel Bea, Hiroyuki Hashimoto, Mariappan Murugesan, Kang-Wook Lee, Tetsu Tanaka, Kazushi Asami, Yasuhiro Kitamura, Mitsumasa Koyanagi. [doi]
- Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applicationsYangyang Yan, Yingtao Ding, Qianwen Chen, Kang-Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi. [doi]
- Warpage analysis of organic substrates for 2.1D packagingSayuri Kohara, Keishi Okamoto, Hirokazu Noma, Kazushige Toriyama, Hiroyuki Mori. [doi]
- 3D-IC technologies and 3D FPGAXin Wu. [doi]
- Neuromorphic semiconductor memoryChung H. Lam. [doi]
- Thermal simulation of heterogeneous GaN/ InP/silicon 3DIC stacksT. Robert Harris, Eric J. Wyers, Lee Wang, Samuel Graham, Georges Pavlidis, Paul D. Franzon, W. Rhett Davis. [doi]
- Modeling and analysis of defects in through silicon via channel for non-invasive fault isolationDaniel H. Jung, Heegon Kim, Jonghoon J. Kim, Sukjin Kim, Joungho Kim, Hyun-Cheol Bae, Kwang-Seong Choi. [doi]
- Guard-ring monitoring system for inspecting defects in TSV-based data busesYuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi. [doi]
- Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layersMasahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto. [doi]
- New precision wafer bonding technologies for 3DICIsao Sugaya, Hajime Mitsuishi, Hidehiro Maeda, Kazuya Okamoto. [doi]
- TSV etching and VDP process integration for high reliabilityTakahide Murayama, Yasuhiro Morikawa. [doi]
- High productivity thermal compression bonding for 3D-ICNoboru Asahi, Yoshinori Miyamoto, Masatsugu Nimura, Yoshihito Mizutani, Yoshiyuki Arai. [doi]
- 3D system integration research at IMECEric Beyne. [doi]
- Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technologyChuei-Tang Wang, Jeng-Shien Hsieh, Victor C. Y. Chang, En-Hsiang Yeh, Feng-Wei Kuo, Hsu-Hsien Chen, Chih-Hua Chen, Ron Chen, Ying-Ta Lu, Chewnpu Jou, Hao-Yi Tsai, C. S. Liu, Doug C. H. Yu. [doi]
- 3D ICs: An opportunity for fully-integrated, dense and efficient power suppliesGaël Pillonnet, Nicolas Jeanniot, Pascal Vivet. [doi]
- Path to 3D heterogeneous integrationDaniel S. Green, Carl L. Dohrman, Jeffrey Demmin, Tsu-Hsi Chang. [doi]
- Temperature-aware online testing of power-delivery TSVsHua-Cheng Fu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou. [doi]
- Copper micro and nano particles mixture for 3D interconnections applicationYuan Yuan Dai, Mei Zhen Ng, P. Anantha, Chee Lip Gan, Chuan Seng Tan. [doi]
- Congestion-aware optimal techniques for assigning inter-tier signals to 3D-vias in a 3DICGopi Neela, Jeffrey Draper. [doi]
- Active Si interposer for 3D IC integrationsJoungho Kim. [doi]
- Stress management strategy to limit die curvature during silicon interposer integrationBenjamin Vianne, Alexis Farcy, Vincent Fiori, C. Chappaz, Norbert Chevrier, G. Lobascio, Pascal Chausse, F. Ponthenier, A. Ruckly, Stephanie Escoubas, O. Thomas. [doi]
- Influential factors in low-temperature direct bonding of silicon dioxideRyouya Shirahama, Sethavut Duangchan, Yusuke Koishikawa, Akiyoshi Baba. [doi]
- Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuitKosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu. [doi]
- Design of a 3-D stacked floating-point Goldschmidt dividerJubee Tada, Ryusuke Egawa, Hiroaki Kobayashi. [doi]
- No pumping at 450°C with electrodeposited copper TSVKazuo Kondo, Shingo Mukahara, Masayuki Yokoi, Jin Onuki. [doi]
- Enabling automatic system design optimization through Assembly Design KitsAndy Heinig, Robert Fischbach. [doi]
- Comprehensive comparison of 3D-TSV integrated solid-state drives (SSDs) with storage class memory and NAND flash memoryShogo Hachiya, Takahiro Onagi, Sheyang Ning, Ken Takeuchi. [doi]
- Current and future 3D activities at FraunhoferAndy Heinig, Muhammad Waqas Chaudhary, Peter Schneider, Peter Ramm, Josef Weber. [doi]
- Electrical investigation of Cu pumping in through-silicon vias for BEOL reliability in 3D integrationChuan-An Cheng, Ryuichi Sugie, Tomoyuki Uchida, Kou-Hua Chen, Chi-Tsung Chiu, Kuan-Neng Chen. [doi]
- Silicon based dry-films evaluation for 2.5D and 3D Wafer-Level system integration improvementAmadine Jouve, Y. Sinquin, Arnaud Garnier, M. Daval, Pascal Chausse, M. Argoud, N. Allouti, Laurence Baud, Jérôme Dechamp, R. Franiatte, Séverine Cheramy, H. Kato, K. Kondo. [doi]
- Investigation of effects of metalization on heat spreading in bump-bonded 3D systemsSamson Melamed, Katsuya Kikuchi, Masahiro Aoyagi. [doi]
- Graphite-based heat spreaders for hotspot mitigation in 3D ICsCristiano Santos, Rafael Prieto, Pascal Vivet, Jean-Philippe Colonna, Perceval Coudrain, Ricardo Reis. [doi]
- Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D ICSumin Choi, Heegon Kim, Daniel H. Jung, Jonghoon J. Kim, Jaemin Lim, Hyunsuk Lee, Kyungjun Cho, Joungho Kim, Hyungsoo Kim, Yongju Kim, Yunsaing Kim. [doi]
- Copper-filled anodized aluminum oxide a potential material for chip to chip bondingKosuke Yamashita, Shunji Kurooka, Koji Shirakawa, Yoshinori Hotta, Hirofumi Abe. [doi]
- High-speed via hole filling using electrophoresis of Ag nanoparticlesRyo Takigawa, Kohei Nitta, Akihiro Ikeda, Mitsuaki Kumazawa, Toshiharu Hirai, Michio Komatsu, Tanemasa Asano. [doi]
- TSV noise coupling in 3D IC using guard ringR. Ranga Reddy, Sugandh Tanna, Shiv Govind Singh, Om Krishna Singh. [doi]
- Characterization of stress distribution in ultra-thinned DRAM waferTomoji Nakamura, Yoriko Mizushima, Young-Suk Kim, Ryuichi Sugie, Takayuki Ohba. [doi]
- Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD studyMariappan Murugesan, Jichoel Bea, H. Hashimoto, K. W. Lee, Mitsu Koyanagi, Takafumi Fukushima, Tetsu Tanaka. [doi]
- Fast filling of through-silicon via (TSV) with conductive polymer/metal compositesJin Kawakita, Barbara Horváth, Toyohiro Chikyow. [doi]
- Best engineering practice for thermal characterization of stacked dice FPGA devicesArun Raghupathy, Hoa Do, Brian Philofsky, Gamal Refai-Ahmed. [doi]
- Air-gap/SiO2 liner TSVs with improved electrical performanceCui Huang, Dong Wu, Liyang Pan, Zheyao Wang. [doi]
- Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integrationKuniaki Sueoka, Akihiro Horibe, T. Aoki, Sayuri Kohara, Kazushige Toriyama, Hiroyuki Mori, Yasumitsu Orii. [doi]
- Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT linerTung T. Bui, Naoya Watanabe, Masahiro Aoyagi, Katsuya Kikuchi. [doi]
- The issues of automated driving vehicle and the expectations for 3D integration technologyTadashi Kamada. [doi]
- Proposed static timing analysis framework for extracted 3D integrated circuits (3D-STA)Mohamed N. ElBahey, DiaaEldin S. Khalil, Hani F. Ragai. [doi]
- Improved access pattern for ROB soft error rate mitigation based on 3D integration technologyChao Song, Minxuan Zhang. [doi]
- Characterization of the mechanical stress impact on device electrical performance in the CMOS and III-V HEMT/HBT heterogeneous integration environmentEric J. Wyers, T. Robert Harris, Wallace Shep Pitts, Jordan E. Massad, Paul D. Franzon. [doi]
- Room-temperature bonding mechanism of compliant bump with ultrasonic assistKeiichiro Iwanabe, Tanemasa Asano. [doi]
- Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layersK. W. Lee, C. Nagai, A. Nakamura, H. Aizawa, Ji Chel Bea, Mitsumasa Koyanagi, Hideto Hashiguchi, Takafumi Fukushima, Tetsu Tanaka. [doi]
- Development of high-quality low-temperature (≤ 120°C) PECVD-SiN films by organosilaneHiroshi Taka, Katsumasa Suzuki, Norihiro Tsujioka, Shoichi Murakami. [doi]
- 3D integration: Applications and market trendsRozalia Beica. [doi]
- Cost modeling and analysis for the design, manufacturing and test of 3D-ICsArmin Gruenewald, Michael Wahl, Rainer Brueck. [doi]
- Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D ICHisashi Kino, Hideto Hashiguchi, Seiya Tanikawa, Yohei Sugawara, Shunsuke Ikegaya, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka. [doi]
- Permanent wafer bonding in the low temperature by using various plasma enhanced chemical vapour deposition dielectricsSoon-Wook Kim, Lan Peng, Andy Miller, Gerald Beyer, Eric Beyne, Chung-Sun Lee. [doi]
- Silicon interposer platform with low-loss through-silicon vias using airHanju Oh, Gary S. May, Muhannad S. Bakir. [doi]
- Processing active devices on Si interposer and impact on costDimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen, Geert Van der Plas, Antonio La Manna, Andy Miller, Dimitri Linten, Eric Beyne. [doi]
- Invited talk: Some challenges in scaling 3D ICs to a broader application setSubramanian Iyer. [doi]