Abstract is missing.
- Novel inter layer dielectric and thermal TSV material for enhanced heat mitigation in 3-D ICKumail Khurram, Asisa Kumar Panigrahi, Satish Bonam, Om Krishan Singh, Shiv Govind Singh. 1-4 [doi]
- Thermal analysis of multi-layer functional 3D logic stacksMichael Scheuermann, S. Tian, Raphael Robertazzi, Matthew R. Wordeman, C. Bergeron, H. Jacobson, Phillip Restle, Joel Silberman, Christy Tyberg. 1-4 [doi]
- A front-illuminated stacked global-shutter CMOS image sensor with multiple chip-on-chip integrationKentaro Akiyama, Yusuke Oike, Yoshiaki Kitano, Junichiro Fjimagari, Wakiyama Satoru, Yorito Sakano, Takayuki Toyama, Hayato Iwamoto, Takayuki Ezaki, Takuya Nakamura, Tetsunori Imaizumi, Nonaka Yasuhiro. 1-3 [doi]
- Interposer based integration to achieve high speed interfaces for ADC applicationMuhammad Waqas Chaudhary, Andy Heinig, Michael Dittrich. 1-4 [doi]
- From 2D to monolithic 3D predictive design platform: An innovative migration methodology for benchmark purposeGerald Cibrario, Nour Ben Salem, Joris Lacord, Karim Azizi-Mourier, Olivier Rozeau, Etienne Maurin, Olivier Billoint, Sebastien Thuries, Alexandre Valentian. 1-5 [doi]
- Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV moduleStefaan Van Huylenbroeck, Yunlong Li, Michele Stucchi, Lieve Bogaerts, Joeri De Vos, Gerald Beyer, Eric Beyne, Mohand Brouri, Praveen Nalla, Sanjay Gopinath, Matthew Thorum, Joe Richardson, Jengyi Yu. 1-4 [doi]
- 3D integration and challenges for advanced RF and microwave systems: EDA perspectiveRosa R. Lahiji, Timothy T. Lee, Warren P. Snapp. 1-2 [doi]
- 3 Dimensional stacked pixel detector and sensor technology using less than 3-μmφ robust bump junctionsMakoto Motoyoshi, Kohki Yanagimura, Taikoh Fushimi, Junichi Takanohashi, Mariappan Murugesan, Masahiro Aoyagi, Mitsumasa Koyanagi. 1-4 [doi]
- 3D floorplan representations: Corner links and partial orderFang Qiao, Ilgweon Kang, Daniel Kane, Fung Yu Young, Chung-Kuan Cheng, Ronald L. Graham. 1-5 [doi]
- Considerations of TSV effects on next-generation super-high-speed transmission and power integrity design for 300A-class 2.5D and 3D package integrationMakoto Suwada, Kazuhiro Kanai. 1-4 [doi]
- New concept of TSV formation methodology using Directed Self-Assembly (DSA)Takafumi Fukushima, Mariappan Murugesan, Shin Ohsaki, Hiroyuki Hashimoto, Jichoel Bea, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
- Design and analysis of on-interposer active power distribution network for an efficient simultaneous switching noise suppression in 2.5D ICSubin Kim, YoungWoo Kim, Kyungjun Cho, Jinwook Song, Joungho Kim. 1-5 [doi]
- Die to wafer 3D stacking for below 10um pitch microbumpsJaber Derakhshandeh, Lin Hou, Inge De Preter, Carine Gerets, Samuel Suhard, Vikas Dubey, Geraldine Jamieson, Fumihiro Inoue, Tomas Webers, Pieter Bex, Giovanni Capuz, Eric Beyne, John Slabbekoorn, Teng Wang, Anne Jourdain, Gerald Beyer, Kenneth June Rebibis, Andy Miller. 1-4 [doi]
- 3D integration and challenges for advanced RF and microwave systems: EDA perspectiveRosa R. Lahiji, Timothy T. Lee, Warren P. Snapp. 1-3 [doi]
- Improved noise coupling performance using optimized Teflon liner with different TSV structures for 3D IC integrationSuraj Patil, Asisa Kumar Panigrahi, Satish Bonam, C. Hemanth Kumar, Om Krishan Singh, Shiv Govind Singh. 1-4 [doi]
- Predicted thermal stresses in a TSV designEphraim Suhir, Sung Yi. 1-4 [doi]
- Wet cleaning process for high-yield via-last TSV formationNaoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi, Hidekazu Kikuchi, Azusa Yanagisawa, Akio Nakamura. 1-4 [doi]
- ITAC: A complete 3D integration test platformDidier Lattard, L. Arnaud, Arnaud Garnier, N. Bresson, Franck Bana, R. Segaud, Amadine Jouve, H. Jacquinot, Stéphane Moreau, Karim Azizi-Mourier, C. Chantre, Pascal Vivet, G. Pillonnet, F. Casset, F. Ponthenier, Alexis Farcy, S. Lhostis, Jean Michailos, Alexandre Arriordaz, Séverine Cheramy. 1-4 [doi]
- Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnectsJoeri De Vos, Lan Peng, Alain Phommahaxay, Joost Van Ongeval, Andy Miller, Eric Beyne, Florian Kurz, Thomas Wagenleiter, Markus Wimplinger, Thomas Uhrmann. 1-5 [doi]
- Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technologyMariappan Murugesan, Jichel Bea, Takafumi Fukushima, Makoto Motoyoshi, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
- Extreme wafer thinning optimization for via-last applicationsAnne Jourdain, Joeri De Vos, Fumihiro Inoue, Kenneth June Rebibis, Andy Miller, Gerald Beyer, Eric Beyne, Edward Walsby, Jash Patel, Oliver Ansell, Janet Hopkins, Huma Ashraf, Dave Thomas. 1-5 [doi]
- The impact of 3D stacking on GPU-accelerated deep neural networks: An experimental studyWilliam Wahby, Thomas E. Sarvey, Hardik Sharma, Hadi Esmaeilzadeh, Muhannad S. Bakir. 1-4 [doi]
- The influence of device morphology on wafer-level bonding with polymer-coated layerHao-Wen Liang, Hsiu-Chi Chen, Chien-Hung Lin, Chia-Lin Lee, Shan-Chun Yang, Kuan-Neng Chen. 1-4 [doi]
- Towards high density 3D interconnectionsSéverine Cheramy, Amandine Jouve, Lucile Arnaud, Claire Fenouillet-Béranger, Perrine Batude, Maud Vinet. 1-2 [doi]
- Towards high density 3D interconnectionsSéverine Cheramy, Amadine Jouve, L. Arnaud, Claire Fenouillet-Béranger, Perrine Batude, Maud Vinet. 1-5 [doi]
- A 3D multi-layer CMOS-RRAM accelerator for neural networkHantao Huang, Leibin Ni, Yuhao Wang, Hao Yu, Zongwei Wang, Yimao Cail, Ru Huangl. 1-5 [doi]
- Copper TSV-based die-level via-last 3D integration process with parylene-C adhesive bonding techniqueS. E. Kucuk Eroglu, W. Y. Choo, Yusuf Leblebici. 1-5 [doi]
- Analysis of graphene and CNT based finned TTSV and spreaders for thermal management in 3D ICSuraj Singh, Asisa Kumar Panigrahi, Om Krishan Singh, Shiv Govind Singh. 1-4 [doi]
- Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processesC. Santos, Pascal Vivet, Sebastien Thuries, Olivier Billoint, Jean-Philippe Colonna, Perceval Coudrain, L. Wang. 1-5 [doi]
- Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-viasYangyang Yan, Ziyue Zhang, Zhiqiang Cheng, Lingfeng Zhou, Zhiming Chen, Yingtao Ding. 1-5 [doi]
- Study of MOSFET thermal stability with TSV in operation temperature using novel 3D-LSI stress analysisHideki Kitada, Hiroko Tashiro, Shoichi Miyahara, Takeshi Ishitsuka, Aki Dote, Shinji Tadaki, Tatsumi Nakada, Seiki Sakuyama. 1-4 [doi]
- Low temperature CMOS compatible Cu-Cu thermo-compression bonding with constantan alloy passivation for 3D IC integrationAsisa Kumar Panigrahi, Satish Bonam, Tamal Ghosh, Siva Rama Krishna Vanjari, Shiv Govind Singh. 1-4 [doi]
- Impact of TSV integration on 14nm FinFET device performanceLuke England, Sukeshwar Kannan, Rahul Agarwal, Daniel Smith. 1-5 [doi]
- Front-side mid-level Tungsten TSV integration for high-density 3D applicationsBrian Mattis, Lovelace Soirez, Catherine Bullock, Dave Martini, Sara Jensen, James Levy, Adam Jones. 1-4 [doi]
- Reliability investigation and mechanism analysis for a novel bonding method of flexible substrate in 3D integrationYu-Tao Yang, Yu-Chen Hu, Kuan-Neng Chen. 1-4 [doi]
- Heat spreading packaging solutions for hybrid bonded 3D-ICsRafael Prieto, Perceval Coudrain, Jean-Philippe Colonna, Y. Hallez, Christian Chancel, V. Rat, Sylvain Dumas, G. Romano, R. Franiatte, C. Brunet-Manquiat, Séverine Cheramy, Alexis Farcy. 1-6 [doi]
- A power-aware LLC control mechanism for the 3D-stacked memory systemRyusuke Egawa, Wataru Uno, Masayuki Sato, Hiroaki Kobayashi, Jubee Tada. 1-4 [doi]
- Physical design of a 3D-stacked heterogeneous multi-core processorRandy Widialaksono, Rangeen Basu Roy Chowdhury, Zhenqian Zhang, Joshua Schabel, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon. 1-5 [doi]
- Design considerations for 2.5-D and 3-D integration accounting for thermal constraintsYang Zhang, Xuchen Zhang, William Wahby, Muhannad S. Bakir. 1-5 [doi]
- High density backside tungsten TSV for 3D stacked ICsReynard Blasa, Brian Mattis, Dave Martini, Sidi Lanee, Carl Petteway, Sangki Hong, Kangsoo Yi. 1-4 [doi]
- Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applicationsKang-Wook Lee, Ai Nakamura, Jicheol Bea, Takafumi Fukushima, Suresh Ramalingam, Xin Wu, Tanaka Tanaka, Mitsumasa Koyanagi. 1-5 [doi]
- Drastic reduction of keep-out-zone in 3D-IC by local stress suppression with negative-CTE fillerHisashi Kino, Takafumi Fukushima, Tetsu Tanaka. 1-4 [doi]
- Analog-digital partitioning and coupling in 3D-IC for RF applicationsGilad Yahalom, Stacy Ho, Alice Wang, Uming Ko, Anantha Chandrakasan. 1-4 [doi]
- 3D TSV based high frequency components for RF IC and RF MEMS applicationsMontserrat Fernandez-Bolaños, Wolfgang A. Vitale, Mariazel Maqueda Lopez, Adrian M. Ionescu, Armin Klumpp, Karl-Reinhard Merkel, Josef Weber, Peter Ramm, Ilja Ocket, Walter De Raedt, Amin Enayati. 1-4 [doi]
- Noise performance improvement through optimized stacked layer of liner structure around the TSV in 3D ICC. Hemanth Kumar, Asisa Kumar Panigrahi, Om Krishan Singh, Shiv Govind Singh. 1-4 [doi]
- Through-substrate via (TSV) with embedded capacitor as an on-chip energy storage elementYe-Lin, Chuan Seng Tan. 1-4 [doi]
- High-density and low-leakage novel embedded 3D MIM capacitor on Si interposerC. Roda Neve, Mikael Detalle, P. Nolmans, Yunlong Li, Joeri De Vos, Geert Van der Plas, Gerald Beyer, Eric Beyne. 1-4 [doi]
- 3DIP: An iterative partitioning tool for monolithic 3D ICGuillaume Berhault, Melanie Brocard, Sebastien Thuries, François Galea, Lilia Zaourar. 1-5 [doi]