Abstract is missing.
- Investigation of optimized high-density flip-chip interconnect design including micro Au bumps for 3-D stacked LSI packagingKatsuya Kikuchi, Fumiki Kato, Shunsuke Nemoto, Hiroshi Nakagawa, Masahiro Aoyagi, Youtaro Yasu, Kohji Koshiji. 1-4 [doi]
- Thermal requirements in future 3D processorsPaul D. Franzon, Avi Bar-Cohen. 1-6 [doi]
- 3D cache hierarchy optimizationLeonid Yavits, Amir Morad, Ran Ginosar. 1-5 [doi]
- Device physics aware 3D electromagnetic simulation of Through-Silicon-Vias in system modelingDipanjan Gope, S. Chatterjee, D. de Araujo, Swagato Chakraborty, J. Pingenot, Raul Camposano. 1-5 [doi]
- The monolithic 3D advantage: Monolithic 3D is far more than just an alternative to 0.7x scalingZvi Or-Bach. 1-7 [doi]
- High density and reliable packaging technology with Non Conductive Film for 3D/TSVKentaro Mori, Yoshihiro Ono, Shinji Watanabe, Toshikazu Ishikawa, Michiaki Sugiyama, Satoshi Imasu, Toshihiko Ochiai, Ryo Mori, Tsuyoshi Kida, Tomoaki Hashimoto, Hideki Tanaka, Michitaka Kimura. 1-7 [doi]
- TSV capacitance aware 3-D floorplanningMohammad A. Ahmed, Malgorzata Chrzanowska-Jeske. 1-6 [doi]
- Thermal correlation between measurements and FEM simulations in 3D ICsP. M. Souare, François de Crecy, Vincent Fiori, H. Ben Jamaa, Alexis Farcy, Sébastien Gallois-Garreignot, A. Borbely, J.-P. Colonna, P. Coudrain, B. Giraud, C. Laviron, Séverine Cheramy, Clément Tavernier, J. Michailos. 1-6 [doi]
- Evaluation of 3DICs and fabrication of monolithic interlayer viasWilliam Wahby, Ashish Dembla, Muhannad Bakir. 1-6 [doi]
- Thermo-mechanical study of a 2.5D passive silicon interposer technology: Experimental, numerical and In-Situ stress sensors developmentsBenjamin Vianne, Pierre Bar, Vincent Fiori, Sebastien Petitdidier, Norbert Chevrier, Sébastien Gallois-Garreignot, Alexis Farcy, Pascal Chausse, Stephanie Escoubas, Nicolas Hotellier, Olivier Thomas. 1-7 [doi]
- Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testingSurajit Kumar Roy, Sobitri Chatterjee, Chandan Giri, Hafizur Rahaman. 1-6 [doi]
- Thermal aware Graphene based Through Silicon Via design for 3D ICNahid M. Hossain, MunEm Hossain, Abdul Hamid Bin Yousuf, Masud H. Chowdhury. 1-4 [doi]
- TSV-based, modular and collision detectable face-to-back shared bus designZhenqian Zhang, Paul D. Franzon. 1-5 [doi]
- Implementing wireless communication links in 3-D ICs utilizing wide-band on-chip meandering microbump antennaJulia Hsin-Lin Lu, Wing-Fai Loke, Dimitrios Peroulis, Byunghoo Jung. 1-5 [doi]
- 3D-IC dynamic thermal analysis with hierarchical and configurable chip thermal modelStephen H. Pan, Norman Chang, Tadaaki Hitomi. 1-8 [doi]
- A 3D-stacked logic-in-memory accelerator for application-specific data intensive computingQiuling Zhu, Berkin Akin, H. Ekin Sumbul, Fazle Sadi, James C. Hoe, Larry Pileggi, Franz Franchetti. 1-7 [doi]
- Vertically integrated processor and memory module design for vector supercomputersRyusuke Egawa, Masayuki Sato, Jubee Tada, Hiroaki Kobayashi. 1-6 [doi]
- Highly efficient TSV repair technology for resilient 3-D stacked multicore processor systemH. Hashimoto, Takafumi Fukushima, Kang-Wook Lee, Mitsumasa Koyanagi, Tetsu Tanaka. 1-5 [doi]
- Dedicated MEMS-based test structure for 3D SiP interconnects reliability investigationTomasz Bieniek, Grzegorz Janczyk, Rafal Dobrowolski, Dariusz Szmigiel, Magdalena Ekwinska, Piotr Grabiec, Pawel Janus, Jerzy Zajac. 1-6 [doi]
- Face-to-face bus design with built-in self-test in 3D ICsZhenqian Zhang, Brandon Noia, Krishnendu Chakrabarty, Paul D. Franzon. 1-7 [doi]
- Development of via-last 3D integration technologies using a new temporary adhesive systemTakafumi Fukushima, Jichoel Bea, Mariappan Murugesan, Kang-Wook Lee, Mitsumasa Koyanagi. 1-4 [doi]
- Very low-voltage swing while high-bandwidth data transmission through 4096 bit TSVsSatoshi Takaya, Makoto Nagata, Hiroaki Ikeda. 1-4 [doi]
- Design of 60 GHz contactless probe system for RDL in passive silicon interposerEdward J. Suh, Paul D. Franzon. 1-5 [doi]
- Eye-diagram simulation and analysis of a high-speed TSV-based channelHeegon Kim, Jonghyun Cho, Jonghoon J. Kim, Daniel H. Jung, Sumin Choi, Joungho Kim, Junho Lee, Kunwoo Park. 1-7 [doi]
- Recent progress in thin wafer processingThomas Uhrmann, Thorsten Matthias, Markus Wimplinger, Jurgen Burggraf, Daniel Burgstaller, Harald Wiesbauer, Paul Lindner. 1-8 [doi]
- Contact testing of copper micro-pillars with very low damage for 3D IC assemblyOnnik Yaglioglu, Ben Eldridge. 1-4 [doi]
- Surface passivation of Cu cone bump by self-assembled-monolayer for room temperature Cu-Cu bondingA. Ikeda, L. J. Qiu, K. Nakahara, T. Asano. 1-4 [doi]
- New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stackingMasahiro Aoyagi, Naoya Watanabe, Motohiro Suzuki, Katsuya Kikuchi, Shunsuke Nemoto, Noriaki Arima, Misaki Ishizuka, Koji Suzuki, Toshio Shiomi. 1-5 [doi]
- A compact 3D silicon interposer package with integrated antenna for 60GHz wireless applicationsY. Lamy, Laurent Dussopt, O. El Bouayadi, C. Ferrandon, Alexandre Siligaris, Cedric Dehos, Pierre Vincent. 1-6 [doi]
- Characterization and optimization of a TSV CMP reveal process using a novel wafer inspection technique for detecting sub-monolayer surface contaminationJason Chew, Uday Mahajan, Rajeev Bajaj, Iad Mirshad, Robert Newcomb. 1-6 [doi]
- Fault isolation of short defect in through silicon via (TSV) based 3D-ICDaniel H. Jung, Jonghyun Cho, Heegon Kim, Jonghoon J. Kim, Hongseok Kim, Joungho Kim, Hyun-Cheol Bae, Kwang-Seong Choi. 1-4 [doi]
- Active pixel sensors with enhanced pixel-level analog and digital functionalities in a 2-tier 3D CMOS technologyValerio Re, Massimo Manghisoni, Gianluca Traversi, Luigi Gaioni, Alessia Manazza, Lodovico Ratti. 1-7 [doi]
- Wafer thinning for 3D integrationRicardo I. Fuentes. 1-5 [doi]
- Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technologyVinod Pangracious, Habib Mehrez, Zied Marrakchi. 1-8 [doi]
- A high-performance multiported L2 memory IP for scalable three-dimensional integrationErfan Azarkhish, Igor Loi, Luca Benini. 1-8 [doi]
- Yield analysis of a novel wafer manipulation method in 3D stackingBei Zhang, Baohu Li, Vishwani D. Agrawal. 1-8 [doi]
- A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensorKouji Kiyoyama, Y. Sato, H. Hashimoto, Kang-Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
- Si interposer build-up options and impact on 3D system costDimitrios Velenis, Mikael Detalle, Erik Jan Marinissen, Eric Beyne. 1-5 [doi]
- Highly conformal and adhesive electroless barrier and Cu seed formation using nanoparticle catalyst for realizing a high aspect ratio cu-filled TSVS. Nishizawa, Ryohei Arima, Tomohiro Shimizu, Shoso Shingubara, Fumihiro Inoue. 1-4 [doi]
- Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin waferJui-Chin Chen, John H. Lau, Tzu-Chien Hsu, Chien-Chou Chen, Pei-Jer Tzeng, Po-Chih Chang, Chun-Hsien Chien, Yiu-Hsiang Chang, Shang-Chun Chen, Yu-Chen Hsin, Sue-Chen Liao, Cha-Hsin Lin, Tzu-Kun Ku, Ming-Jer Kao. 1-5 [doi]
- Low temperature (<180 °C) bonding for 3D integrationYan-Pin Huang, Ruoh-Ning Tzeng, Yu-San Chien, Ming-Shaw Shy, Teu-Hua Lin, Kuo-Hua Chen, Ching-Te Chuang, Wei Hwang, Chi-Tsung Chiu, Ho-Ming Tong, Kuan-Neng Chen. 1-5 [doi]
- 3D integration of standard integrated circuitsRene Puschmann, Mathias Bottcher, Irene Bartusseck, Frank Windrich, Conny Fiedler, Peggy John, Charles Alix Manier, Kai Zoschke, Jurgen Grafe, Hermann Oppermann, Jürgen Wolf, K. Dieter Lang, Michael Ziesmann. 1-7 [doi]
- Pulsed laser annealing: A scalable and practical technology for monolithic 3D ICBipin Rajendran, Albert K. Henning, Brian Cronquist, Zvi Or-Bach. 1-5 [doi]
- Design of a 3-D stacked floating-point adderJubee Tada, Ryusuke Egawa, Hiroaki Kobayashi. 1-4 [doi]
- System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuitCristiano Santos, Pascal Vivet, Denis Dutoit, Philippe Garrault, Nicolas Peltier, Ricardo Reis. 1-6 [doi]
- High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposerJiacheng Wang, Shunli Ma, Sai Manoj Pudukotai Dinakarrao, Mingbin Yu, Roshan Weerasekera, Hao Yu. 1-4 [doi]
- Optimal stacking of SOCs in a 3D-SIC for post-bond testingManjari Pradhan, Chandan Giri, Hafizur Rahaman, Debesh K. Das. 1-5 [doi]
- Design of controller for L2 cache mapped in Tezzaron stacked DRAMNyunyi M. Tshibangu, Paul D. Franzon, Eric Rotenberg, William Rhett Davis. 1-4 [doi]
- Chip to wafer copper direct bonding electrical characterization and thermal cyclingYann Beilliard, Perceval Coudrain, Léa Di Cioccio, Stephane Moreau, Loic Sanchez, Brigitte Montmayeul, Thomas Signamarcheix, Rafael Estevez, Guillaume Parry. 1-7 [doi]
- Non-contact wafer-level TSV connectivity test methodology using magnetic couplingJonghoon J. Kim, Heegon Kim, Sukjin Kim, Bumhee Bae, Daniel H. Jung, Sunkyu Kong, Joungho Kim, Junho Lee, Kunwoo Park. 1-4 [doi]
- Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integrationS. Joblot, Alexis Farcy, Nicolas Hotellier, Amadine Jouve, François de Crecy, A. Garnier, M. Argoud, C. Ferrandon, J.-P. Colonna, R. Franiatte, C. Laviron, Séverine Cheramy. 1-7 [doi]
- Analysis of glass interposer PDN and proposal of PDN resonance suppression methodsJonghyun Cho, YoungWoo Kim, Joungho Kim, Venky Sundaram, Rao R. Tummala. 1-5 [doi]
- Integration of CNT in TSV (≤5 μm) for 3D IC application and its process challengesK. Ghosh, C. C. Yap, B. K. Tay, C. S. Tan. 1-4 [doi]
- 3D X-ray microscopy: A near-SEM non-destructive imaging technology used in the development of 3D IC packagingYuri Sylvester, Luke Hunter, Bruce Johnson, Raleigh Estrada. 1-7 [doi]
- Using 3D-COSTAR for 2.5D test cost optimizationMottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik. 1-8 [doi]
- Cost-effective temporary bonding and debonding material solution towards high-volume manufacturing 2.5D/3D through-silicon via integrated circuitsYann Civale, Herman Meynen, Ranjith S. E. John, Peng-Fei Fu, Craig R. Yeakle, Sheng Wang, Stefan Krausse, Thomas Rapps, Stefan Lutter. 1-5 [doi]
- Glass interposer with high-density three-dimensional structured TGV for 3D system integrationOsamu Nukaga, Tatsuya Shioiri, Satoshi Yamamoto, Tatsuo Suemasu. 1-4 [doi]
- Which interconnects for which 3D applications? Status and perspectivesY. Lamy, J.-P. Colonna, G. Simon, Patrick Leduc, Séverine Cheramy, C. Laviron. 1-6 [doi]
- Front to backside alignment for TSV based 3D integrationFrank Windrich, Andreas Schenke. 1-6 [doi]
- The development and evaluation of RF TSV for 3D IPD applicationsThorbjorn Ebefors, Jessica Fredlund, Daniel Perttu, Raymond van Dijk, Lorenzo Cifola, Mikko Kaunisto, Pekka Rantakari, Tauno Vaha-Heikkila. 1-8 [doi]
- Detailed electrical and reliability study of tapered TSVsTiantao Lu, Ankur Srivastava. 1-7 [doi]
- Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stackKeiji Matsumoto, Soichiro Ibaraki, Kuniaki Sueoka, Katsuyuki Sakuma, Hidekazu Kikuchi, Hiroyuki Mori, Yasumitsu Orii, Fumiaki Yamada, Kohei Fujihara, Junichi Takamatsu, Koji Kondo. 1-8 [doi]
- Influence of wafer thinning process on backside damage in 3D integrationTadao Nakamura, Y. Mizushima, H. Kitada, Y. S. Kim, N. Maeda, S. Kodama, R. Sugie, Hiroshi Hashimoto, A. Kawai, K. Arai, A. Uedono, T. Ohba. 1-6 [doi]
- Within-tier cooling and thermal isolation technologies for heterogeneous 3D ICsYue Zhang, Hanju Oh, Muhannad S. Bakir. 1-6 [doi]
- Performance and process characteristic of glass interposer with through-glass-via(TGV)Chun-Hsien Chien, Hsun Yu, Ching-Kuan Lee, Yu-Min Lin, Ren-Shin Cheng, Chau-Jie Zhan, Peng-Shu Chen, Chang-Chih Liu, Chao-Kai Hsu, Hsiang-Hung Chang, Huan-Chun Fu, Yuan-Chang Lee, Wen-Wei Shen, Cheng-Ta Ko, Wei-Chung Lo, Yung Jean Lu. 1-7 [doi]
- Characterization and optimization of a TSV CMP reveal process using a novel wafer inspection technique for detecting sub-monolayer surface contaminationJason Chew, Uday Mahajan, Rajeev Bajaj, Iad Mirshad, Robert Newcomb. 1-6 [doi]
- High reliability insert-bump bonding process for 3D integrationJun-Yeob Song, Jae-Hak Lee, Hyoung-Joon Kim, Chang Woo Lee, Tae Ho Ha. 1-4 [doi]
- A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patternsAwet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Axel Jantsch, Hannu Tenhunen. 1-5 [doi]
- Analysis of glass interposer PDN and proposal of PDN resonance suppression methodsJonghyun Cho, YoungWoo Kim, Joungho Kim, Venky Sundaram, Rao R. Tummala. 1-5 [doi]
- A 3D Process Design Kit generator based on customizable 3D layout design environmentG. Cibrario, D. Henry, C. Chantre, R. Cuchet, A. Berthelot, K. Azizi-Mourier, M. Gary, F. Gays. 1-5 [doi]
- Test-TSV estimation during 3D-IC partitioningShreepad Panth, Kambiz Samadi, Sung Kyu Lim. 1-7 [doi]
- High density interconnect bonding of heterogeneous materials using non-collapsible microbumps at 10 μm pitchMatthew Lueck, Chris W. Gregory, Dean Malta, Alan Huffman, John M. Lannon, Dorota Temple. 1-5 [doi]
- Layout dependent synthesis for manufacturing costs optimized 3D integrated systemsAndy Heinig. 1-6 [doi]
- Improving 3D-Floorplanning using smart selection operations in meta-heuristic optimizationArtur Quiring, Markus Olbrich, Erich Barke. 1-6 [doi]
- The dependency of TSV keep-out zone (KOZ) on Si crystal direction and liner materialJ. Zhang, L. Zhang, Y. Dong, H. Y. Li, C. M. Tan, G. Xia, C. S. Tan. 1-5 [doi]
- Thermo-mechanical evaluation of 3D packagesSayuri Kohara, Akihiro Horibe, Kuniaki Sueoka, Keiji Matsumoto, Fumiaki Yamada, Hiroyuki Mori, Yasumitsu Orii. 1-4 [doi]
- RF characterization of substrate coupling between TSV and MOS transistors in 3D integrated circuitsMelanie Brocard, Cédric Bermond, Thierry Lacrevaz, Alexis Farcy, Patrick Le Maitre, P. Scheer, Patrick Leduc, Séverine Cheramy, Bernard Fléchet. 1-8 [doi]
- Phase detection based data prefetching for utilizing memory bandwidth of 3D integrated circuitsHong-Yeol Lim, Min-Kwan Kee, Gi-Ho Park. 1-5 [doi]
- Quality in 3D assembly - Is "Known Good Die" good enough?James Quinn, Barbara Loferer. 1-5 [doi]
- A novel circuit model for multiple Through Silicon Vias (TSVs) in 3D ICYang Yi, Yaping Zhou. 1-4 [doi]
- High performance 3D stacked DRAM processor architectures with micro-fluidic coolingCaleb Serafy, Bing Shi, Ankur Srivastava, Donald Yeung. 1-8 [doi]
- Effect of CVD Mn oxide layer as Cu diffusion barrier for TSVMariappan Murugesan, Jichoel Bea, Kang-Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi, Y. Sutou, H. Wang, J. Koike. 1-4 [doi]
- Techniques for assigning inter-tier signals to bondpoints in a face-to-face bonded 3DICNeela Gopi, Jeffrey Draper. 1-6 [doi]
- Thermal analysis and modeling of 3D integrated circuits for test schedulingIndira Rawat, M. K. Gupta, Virendra Singh. 1-5 [doi]
- A study on wafer level TSV build-up integration methodJae-Hak Lee, Hyoung-Joon Kim, Jun-Yeob Song, Chang Woo Lee, Tae Ho Ha. 1-4 [doi]
- 3D memory chip stacking by multi-layer self-assembly technologyTakafumi Fukushima, Jichoel Bea, Mariappan Murugesan, H.-Y. Son, M.-S. Suh, K.-Y. Byun, N.-S. Kim, Kang-Wook Lee, Mitsumasa Koyanagi. 1-4 [doi]
- Integration of intra chip stack fluidic cooling using thin-layer solder bondingYassir Madhour, Michael Zervas, Gerd Schlottig, Thomas Brunschwiler, Yusuf Leblebici, John Richard Thome, Bruno Michel. 1-8 [doi]
- Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memoryKang-Wook Lee, S. Tanikawa, Mariappan Murugesan, H. Naganuma, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
- Silicon Etch with integrated metrology for through silicon via (TSV) revealLaura B. Mauer, John Taddei, Elena Lawrence, Ramey Youssef, Stephen P. Olson. 1-4 [doi]