A 75-GHz PLL in 90-nm CMOS Technology

Jri Lee. A 75-GHz PLL in 90-nm CMOS Technology. In 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007. pages 432-613, IEEE, 2007. [doi]

Abstract

Abstract is missing.