A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability

Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno. A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability. In 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007. pages 174-594, IEEE, 2007. [doi]

Abstract

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