Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi. Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. In Manfred Glesner, Ricardo Augusto da Luz Reis, Hans Eveking, Vincent John Mooney III, Leandro Soares Indrusiak, Peter Zipf, editors, IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003. pages 215-220, Technische Universität Darmstadt, Insitute of Microelectronic Systems, 2003.
Abstract is missing.