Table of Contents

• Architectural Challenges for the Next Decade Integrated PlatformsAndrea Cuomo. 1 [doi]
• Analysis of High-Speed Logic FamiliesG. Privitera, Francesco Pessolano. 2-10 [doi]
• Low-Voltage, Double-Edge-Triggered Flip FlopPradeep Varma, Ashutosh Chakraborty. 11-20 [doi]
• A Genetic Bus Encoding Technique for Power Optimization of Embedded SystemsGiuseppe Ascia, Vincenzo Catania, Maurizio Palesi. 21-30 [doi]
• State Encoding for Low-Power FSMs in FPGALuis Mengibar, Luis Entrena, Michael G. Lorenz, Raul Sánchez-Reillo. 31-40 [doi]
• Reduced Leverage of Dual Supply voltages in Ultra Deep Submicron TechnologiesTim Schoenauer, Jörg Berthold, Christoph Heer. 41-50 [doi]
• A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS GatesJosé Luis Rosselló, Jaume Segura. 51-59 [doi]
• CMOS Gate Sizing under Delay ConstraintAlexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne. 60-69 [doi]
• Process Characterization for Low VTH and Low Power DesignE. Seebacher, Gerhard Rappitsch, H. Höller. 70-79 [doi]
• Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental ResultsJosep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodriguez-Sánchez. 80-89 [doi]
• Effects of Temperature in Deep-Submicron Global Interconnect OptimizationMario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni. 90-100 [doi]
• Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated CircuitsJérôme Lescot, François J. R. Clément. 101-110 [doi]
• Estimation of Crosstalk Noise for On-Chip BusesSampo Tuuna, Jouni Isoaho. 111-120 [doi]
• A Block-Based Approach for SoC Global Interconnect Electrical Parameters CharacterizationM. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni. 121-130 [doi]
• Interconnect Driven Low Power High-Level SynthesisAnsgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel. 131-140 [doi]
• Bridging Clock Domains by Synchronizing the Mice in the MousetrapJoep L. W. Kessels, Ad M. G. Peeters, Suk-Jin Kim. 141-150 [doi]
• Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path UnequalizationSonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida. 151-160 [doi]
• New GALS Technique for Datapath ArchitecturesMilos Krstic, Eckhard Grass. 161-170 [doi]
• Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous AddersJoão Leonardo Fragoso, Gilles Sicard, Marc Renaudin. 171-180 [doi]
• Statistic Implementation of QDI Asynchronous PrimitivesPhilippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin. 181-191 [doi]
• The Emergency of Design for Energy Efficiency: An EDA PerspectiveAntun Domic. 192 [doi]
• The Most Complete Mixed-Signal Simulation Solution with ADVance MSJean Oudinot. 193 [doi]
• Signal Integrity and Power Supply Network Analysis of Deep SubMicron ChipsLouis Scheffer. 194 [doi]
• Power Management in Synopsys Galaxy Design Platform195 [doi]
• Open Multimedia Platform for Next-Generation Mobile Devices196 [doi]
• Statistical Power Estimation of Behavioral DescriptionsB. Arts, N. van der Eng, Marc J. M. Heijligers, H. Munk, Frans Theeuwen, Luca Benini, Enrico Macii, A. Milia, Roberto Maro, A. Bellu. 197-207 [doi]
• A Statistic Power Model for Non-synthetic RTL OperatorsMaurizio Bruno, Alberto Macii, Massimo Poncino. 208-218 [doi]
• Energy Efficient Register RenamingGurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose. 219-228 [doi]
• Stand-by Power Reduction for Storage CircuitsS. Cservany, Jean-Marc Masgonty, Christian Piguet. 229-238 [doi]
• A Unified Framework for Power-Aware Design of Embedded SystemsJosé L. Ayala, Marisa Luisa López-Vallejo. 239-248 [doi]
• A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded SystemsGianluca Palermo, Cristina Silvano, Vittorio Zaccaria. 249-258 [doi]
• High Level Area and Current EstimationFei Li, Lei He, Joseph M. Basile, Rakesh Patel, Hema Ramamurthy. 259-268 [doi]
• Switching Activity Estimation in Non-linear ArchitecturesAlberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner. 269-278 [doi]
• Instruction Level Energy Modeling for Pipelined ProcessorsSpiridon Nikolaidis, Nikolaos Kavvadias, T. Laopoulos, Labros Bisdounis, Spyros Blionas. 279-288 [doi]
• Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary LevelMarc Leeman, David Atienza, Francky Catthoor, Vincenzo De Florio, Geert Deconinck, Jose Manuel Mendias, Rudy Lauwereins. 289-298 [doi]
• An Adiabatic Charge Pump Based Charge Recycling Design StyleVineela Manne, Akhilesh Tyagi. 299-308 [doi]
• Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor SizingJürgen Fischer, Ettore Amirante, Francesco Randazzo, Giuseppe Iannaccone, Doris Schmitt-Landsiedel. 309-318 [doi]
• Low Power Response Time Accelerator with Full Resolution for LCD PanelTae-Chan Kim, Meejoung Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim. 319-327 [doi]
• Memory Compaction and Power Optimization for Wavelet-Based CodersV. Ferentinos, M. Milia, Gauthier Lafruit, Jan Bormans, Francky Catthoor. 328-337 [doi]
• Design Space Exploration and Trade-Offs in Analog Amplifier DesignEmil Hjalmarson, Robert Hägglund, Lars Wanhammar. 338-347 [doi]
• Power and Timing Driven Physical Design AutomationRicardo Augusto da Luz Reis. 348-357 [doi]
• Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless NetworksRamesh Karri, Piyush Mishra. 358-368 [doi]
• Remote Power Control of Wireless Network InterfacesAndrea Acquaviva, Tajana Simunic, Vinay Deolalikar, Sumit Roy. 369-378 [doi]
• Architecture-Driven Voltage Scaling for High-Throughput Turbo-DecodersFrank Gilbert, Norbert Wehn. 379-388 [doi]
• A Fully Digital Numerical-Controlled-OscillatorSeyed Reza Abdollahi, B. Bakkaloglu, S. K. Hosseini. 389-398 [doi]
• Energy Optimization of High-Performance CircuitsHoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija. 399-408 [doi]
• Instruction Buffering Exploration for Low Energy Embedded ProcessorsTom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor. 409-419 [doi]
• Power-Aware Branch Predictor Update for High-Performance ProcessorsAmirali Baniasadi. 420-429 [doi]
• Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable PlatformsKonstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas. 430-439 [doi]
• High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 EncoderMassimo Ravasi, Marco Mattavelli, Paul R. Schumacher, Robert D. Turney. 440-450 [doi]
• Metric Definition for Circuit Speed OptimizationXavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne. 451-460 [doi]
• Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI TechnologiesGrzegorz Tosik, Frédéric Gaffiot, Zbigniew Lisik, Ian O Connor, Faress Tissafi-Drissi. 461-470 [doi]
• An Asynchronous Viterbi Decoder for Low-Power ApplicationsBahman Javadi, Mohsen Naderi, Hossein Pedram, Ali Afzali-Kusha, Mohammad K. Akbari. 471-480 [doi]
• Analysis of the Contribution of Interconnect Effects in the Energy Dissipation of VLSI CircuitsEugeni Isern, Miquel Roca, Francesc Moll. 481-490 [doi]
• A New Hybrid CBL-CMOS Cell for Optimum Noise/Power ApplicationRaúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta. 491-500 [doi]
• Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS CircuitsDavid Guerrero, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán. 501-510 [doi]
• A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing BlockagesDongsheng Wang, Peter Suaris, Nan-Chi Chou. 511-519 [doi]
• Frequent Value Cache for Low-Power Asynchronous Dual-Rail BusByung-Soo Choi, Dong-Ik Lee. 520-529 [doi]
• Reducing Static Energy of Cache Memories via Prediction-Table-Less Way PredictionAkihito Sakanaka, Toshinori Sato. 530-539 [doi]
• A Bottom-Up Approach to On-Chip Signal IntegrityAndrea Acquaviva, Alessandro Bogliolo. 540-549 [doi]
• Advanced Cell Modeling Techniques Based on Polynomial ExpressionsWen-Tsong Shiue, Weetit Wanalertlak. 550-558 [doi]
• RTL-Based Signal Statistics Calculation Facilitates Low Power Design ApproachesPaul Flugger. 559-568 [doi]
• Data Dependences Critical Path Evaluation at C/C++ System Level DescriptionAnatoly Prihozhy, Marco Mattavelli, Daniel Mlynek. 569-579 [doi]
• A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance RequirementsJavier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién. 580-589 [doi]
• Consideration of Control System and Memory Contributions in Practical Resource-Constrained Scheduling for Low PowerChee Lee, Wen-Tsong Shiue. 590-598 [doi]
• Low Power Cache with Successive Tag Comparison AlgorithmTae-Chan Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim. 599-606 [doi]
• FPGA Architecture Design and Toolset for Logic ImplementationKonstantinos Tatas, K. Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis. 607-616 [doi]
• Bit-Level Allocation for Low Power in Behavioural High-Level SynthesisMaría C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida. 617-627 [doi]