Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne. CMOS Gate Sizing under Delay Constraint. In Jorge Juan-Chico, Enrico Macii, editors, Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings. Volume 2799 of Lecture Notes in Computer Science, pages 60-69, Springer, 2003. [doi]
Abstract is missing.