Table of Contents

• On-FPGA Communication Architectures and Design FactorsTerrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk. 1-8 [doi]
• Modular Partitioning for Incremental CompilationMehrdad Eslami Dehkordi, Stephen Dean Brown, Terry Borer. 1-6 [doi]
• Placing Functionality in Fault-Tolerant Hardware/Software Reconfigurable NetworksThilo Streichert. 1-2 [doi]
• Shift-Or Circuit for Efficient Network Intrusion Detection Pattern MatchingHuang-Chun Roan, Wen-Jyi Hwang, Chia-Tien Dan Lo. 1-6 [doi]
• General Digit Width Normal Basis Multipliers with Circular and Linear StructureMartin Novotný, Jan Schmidt. 1-4 [doi]
• On Buffer Management Strategies for High Performance Computing with Reconfigurable HardwareGuillermo Marcus Martinez, Gerhard Lienhart, Andreas Kugel, Reinhard Männer. 1-6 [doi]
• Rapid System-on-a-Programmable-Chip Development and Hardware Acceleration Of ANSI C FunctionsDavid J. Lau, Orion Pritchard. 1-6 [doi]
• A Scalable Network ASIP Enabling Flow Awareness in Ethernet AccessK. Van Renterghem, Dieter Verhulst, S. Verschuere, P. Demuytere, Jan Vandewege, Xing-Zhi Qiu. 1-4 [doi]
• Configware Design Space Exploration Using Rewriting LogicCarlos Morra. 1-2 [doi]
• A Biologically Inspired FPGA Based Implementation of a Tactile Sensory System for Object Recognition and Texture DiscriminationMartin J. Pearson, Mokhtar Nibouche, Anthony G. Pipe, Chris Melhuish, Ian Gilhespy, Benjamin Mitchinson, Kevin N. Gurney, Tony J. Prescott, Peter Redgrave. 1-4 [doi]
• Multi-layer Floorplanning on a Sequence of Reconfigurable DesignsLove Singhal, Elaheh Bozorgzadeh. 1-8 [doi]
• Real-Time Video Pixel MatchingJean-Baptiste Note, Mark Shand, Jean Vuillemin. 1-6 [doi]
• Defect-Tolerant FPGA Architecture ExplorationPongstorn Maidee, Kia Bazargan. 1-6 [doi]
• Perfecto: A Systemc-Based Performance Evaluation Framework for Dynamically Partially Reconfigurable SystemsPao-Ann Hsiung, Chun-Hsian Huang, Chih-Feng Liao. 1-6 [doi]
• A Novel Heuristic and Provable Bounds for Reconfigurable Architecture DesignAlastair M. Smith, George A. Constantinides, Peter Y. K. Cheung. 1-6 [doi]
• Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable DevicesJames Moscola, Young H. Cho, John W. Lockwood. 1-4 [doi]
• Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGAAri Kulmala, Timo D. Hämäläinen, Marko Hännikäinen. 1-6 [doi]
• Multi Stream Cipher Architecture for Reconfigurable System-on-ChipChin Mun Wee, Peter R. Sutton, Neil W. Bergmann, John A. Williams. 1-4 [doi]
• The Darpa Multiple Precision Arithmetic Benchmark on a Reconfigurable ComputerCao Zhang, Duncan A. Buell, Allen Michalski. 1-4 [doi]
• Sizing of Processing Arrays for FPGA-Based ComputationTom Van Court, Martin C. Herbordt. 1-6 [doi]
• Detection Module in a Complementary Set of Sequences-Based Pulse Compression SystemFernando J. Álvarez, Álvaro Hernández, Jesús Ureña, Juan Jesús García, Ana Jiménez, P. Santa Teresa. 1-6 [doi]
• High Speed Document Clustering in Reconfigurable HardwareG. Adam Covington, Charles L. G. Comstock, Andrew A. Levine, John W. Lockwood, Young H. Cho. 1-7 [doi]
• A Scalable Architecture for RSA Cryptography on Large FPGAsAllen Michalski, Duncan A. Buell. 1-8 [doi]
• Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible ProcessorK. S. Tham, Douglas L. Maskell. 1-6 [doi]
• Mapping Recursive Functions to Reconfigurable HardwareGeorge Ferizis, Hossam A. ElGindy. 1-6 [doi]
• FPGA Implementation and Power Modelling of the Fast Walsh TransformShrutisagar Chandrasekaran, Abbes Amira. 1-4 [doi]
• On Feasibility of FPGA Bitstream Compression During Placement and RoutingPiotr Stepien, Milan Vasilko. 1-4 [doi]
• Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault ModelsJan Torben Weinkopf, Klaus Harbich, Erich Barke. 1-6 [doi]
• FPGA Implementation of 3-D Thermal Model SimulatorFernando Pardo, P. López, Diego Cabello, M. Balsi. 1-4 [doi]
• An FPGA Solver for Large SAT ProblemsKenji Kanazawa, Tsutomu Maruyama. 1-6 [doi]
• A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic MemoryMinoru Watanabe, Fuminori Kobayashi. 1-6 [doi]
• FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis AttacksFrançois-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater. 1-4 [doi]
• Executing Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time ConditionsKlaus Danne, Roland Muhlenbernd, Marco Platzner. 1-6 [doi]
• Architecture and CAD for FPGA Clock NetworksJulien Lamoureux, Steven J. E. Wilton. 1-2 [doi]
• A Dynamic Reconfigurable Fabric for Platform SoCsChristos A. Papachristou, J. Weaver, R. Vijayakumar, Francis G. Wolff. 1-4 [doi]
• Synthesis on FPAA of a Smart Sthetoscope Analog SubsystemGinés Doménech-Asensi, Juan Martínez-Alajarín, Ramón Ruiz Merino, José-Alejandro López Alcantud. 1-5 [doi]
• Automation of IP Core Interface Generation for Reconfigurable ComputingZhi Guo, Abhishek Mitra, Walid A. Najjar. 1-6 [doi]
• Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA ChipsHristo Nikolov, Todor Stefanov, Ed F. Deprettere. 1-6 [doi]
• Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System SupportHayden Kwok-Hay So, Robert W. Brodersen. 1-6 [doi]
• A Segmentation Model for Partial Run-Time ReconfigurationMohamed Taher, Tarek A. El-Ghazawi. 1-4 [doi]
• Reconfigurable Architectures for Curve-Based Cryptography on Embedded Micro-ControllersLejla Batina, Alireza Hodjat, David Hwang, Kazuo Sakiyama, Ingrid Verbauwhede. 1-4 [doi]
• Multi-Bit Carry Chains for High-Performance Reconfigurable FabricsMichael T. Frederick, Arun K. Somani. 1-6 [doi]
• An FPGA Implementation of K-Means Clustering for Color Images Based on Kd-TreeTakashi Saegusa, Tsutomu Maruyama. 1-6 [doi]
• A Dual Cache for Performance and Energy Aware Reconfigurable HWElena Perez Ramo, Javier Resano. 1-2 [doi]
• A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible ProcessorHamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani. 1-4 [doi]
• FPGA Based Imaging Particle Detector Trigger SystemGustavo Martinez, Jesus Marin, Carlos Willmott. 1-4 [doi]
• A-B Nodes Classification for Power EstimationElias Todorovich, Eduardo I. Boemo. 1-6 [doi]
• FPGA-Based Boundary-Scan BistAngel Quiros Olozabal, Ma de los Angeles Cifredo Chacon, Diego Gomez Vela. 1-4 [doi]
• High-Performance and Parameterized Matrix Factorization on FPGAsLing Zhuo, Viktor K. Prasanna. 1-6 [doi]
• FPGA Implementation of an Efficient Correlator for Complementary Sets of SequencesMaría del Carmen Pérez, Jesús Ureña, Álvaro Hernández, Carlos De Marziani, A. Ochoa, William P. Marnane. 1-4 [doi]
• Adaptive FPGAs: High-Level Architecture and a Synthesis MethodValavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic. 1-8 [doi]
• An FPGA-Based Electronic Cochlea with Dual Fixed-Point ArithmeticC. K. Wong, Philip Heng Wai Leong. 1-6 [doi]
• Fpga-Oriented Secure Data Path Design: Implementation of a Public Key CoprocessorNele Mentens, Kazuo Sakiyama, Lejla Batina, Ingrid Verbauwhede, Bart Preneel. 1-6 [doi]
• Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design TechniqueTom Van Court, Martin C. Herbordt. 1-7 [doi]
• FPGA Based Architectures for H. 264/AVC Video Compression StandardLuciano Volcan Agostini, Sergio Bampi. 1-2 [doi]
• A Reconfigurable Viterbi Decoder for a Communication PlatformImran Ahmed, Tughrul Arslan. 1-6 [doi]
• An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable ArchitecturesSajid Baloch, Tughrul Arslan, Adrian Stoica. 1-4 [doi]
• A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design VerificationLesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow. 1-6 [doi]
• Area-Efficient Implementation of a Pulse-Mode Neuron ModelCesar Torres-Huitzil. 1-4 [doi]
• IPP Watermarking Technique for IP Core Protection on FPL DevicesEncarnación Castillo, Luis Parrilla, Antonio García, Antonio Lloris-Ruíz, Uwe Meyer-Bäse. 1-6 [doi]
• Fault Tolerant Reconfigurable Device Based on Autonomous-Repair CellsKentaro Nakahara, Shin ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura. 1-6 [doi]
• Reconfigurable Systems Enabled by a Network-on-ChipLeandro Möller, Ismael Grehs, Ney Calazans, Fernando Moraes. 1-4 [doi]
• Efficient Realtime FPGA Implementation of the Trace TransformSuhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk. 1-6 [doi]
• An FPGA Implementation of Pattern-Selective Pyramidal Image FusionOliver Sims, James Irvine. 1-4 [doi]
• Tutorial: 65 NM FPGAs, A Look Under the Hood Technology, Features, and ApplicationsPeter Alfke. 1 [doi]
• A Codesign Tool for High Level Systhesis of Vision Models on FPLAntonio Martínez, Leonardo Maria Reyneri, Francisco J. Pelayo, Christian A. Morillas, Samuel F. Romero. 1-4 [doi]
• Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAsFrancisco-Javier Veredas, Hans-Jörg Pfleiderer. 1-2 [doi]
• Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage StructuresNastaran Baradaran, Pedro C. Diniz. 1-6 [doi]
• Secure Content Distribution System Based on Run-Time Partial Hardware ReconfigurationYohei Hori, Hiroyuki Yokoyama, Kenji Toda. 1-4 [doi]
• Self-Reconfigurable Pervasive Platform for Cryptographic ApplicationArnaud Lagger, Andres Upegui, Eduardo Sanchez, Ivan Gonzalez. 1-4 [doi]
• FPGA Implementation of a Change-Driven Image Processing Architecture for Optical Flow ComputationJulio C. Sosa, Rocio Gomez-Fabela, Jose Antonio Boluda, Fernando Pardo. 1-4 [doi]
• TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAsManuel Saldaña, Paul Chow. 1-6 [doi]
• Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control SystemsYana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly. 1-4 [doi]
• Fast Emulation of Permanent Faults in VLSI SystemsDavid de Andrés, Juan Carlos Ruiz, Daniel Gil, Pedro J. Gil. 1-6 [doi]
• Power Optimization Techniques for SRAM-Based FPGAsSomsubhra Mondal, Seda Ogrenci Memik. 1-2 [doi]
• Using Reconfigurable HW for High Dimensional CAF ComputationAntonin Hermanek, Michal Kunes, Michal Kvasnicka. 1-4 [doi]
• Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design ToolsXin Wang, Tapani Ahonen, Jari Nurmi. 1-6 [doi]
• Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic UnitPedro C. Diniz, Gokul Govindu. 1-4 [doi]
• A Multi-Context Pipelined Array for Embedded SystemsAndrea Lodi 0002, Claudio Mucci, Massimo Bocchi, Andrea Cappelli, Mario de Dominicis, Luca Ciccarelli. 1-8 [doi]
• A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer RegimeKazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera. 1-4 [doi]
• Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAsMichael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert. 1-6 [doi]
• Regular Expression Software Deceleration for Intrusion Detection SystemsZachary K. Baker, Viktor K. Prasanna, Hong-Jip Jung. 1-8 [doi]
• RAID 6 Hardware AccelerationMichael Gilroy, James Irvine. 1-6 [doi]
• Academia to IPO - A Modern OdysseyIan Page. 1 [doi]
• FPGA Performance Optimization Via Chipwise Placement Considering Process VariationsLerong Cheng, Jinjun Xiong, Lei He, Mike Hutton. 1-6 [doi]
• Performance Evaluation of a Preloading Model in Dynamically Reconfigurable ProcessorsKyprianos Papademetriou, Apostolos Dollas. 1-4 [doi]
• DIMMnet-2: A Reconfigurable Board Connected Into a Memory SlotTomotaka Miyashiro, Akira Kitamura, Hironori Nakajo, Noboru Tanabe. 1-4 [doi]
• Power Reduction for FPGA Implementations : Design Optimisation and High Level ModellingShrutisagar Chandrasekaran, Abbes Amira. 1-2 [doi]
• Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAsNicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko. 1-6 [doi]
• Implementation in Fpgas of Jacobi Method to Solve the Eigenvalue and Eigenvector ProblemIgnacio Bravo, Pedro Jiménez, Manuel Mazo, José Luis Lázaro, Alfredo Gardel. 1-4 [doi]
• A Leak Resistant Architecture Against Side Channel AttacksDaniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Jean-Claude Bajard, Fernando Gehm Moraes. 1-4 [doi]
• Non-Uniform Random Number Generation Through Piecewise Linear ApproximationsDavid B. Thomas, Wayne Luk. 1-6 [doi]
• Verification and FPGA Circuits of a Block-2 Fast Path-Based PredictorOswaldo Cadenas, Graham M. Megson. 1-6 [doi]
• A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and EvaluationMário P. Véstias, Horácio C. Neto. 1-4 [doi]
• Actual-Delay Circuits on FPGA: Trading-Off Luts for SpeedEvangelia Kassapaki, Pavlos M. Mattheakis, Christos P. Sotiriou. 1-6 [doi]
• FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual CortexChristos-Savvas Bouganis, Peter Y. K. Cheung, Li Zhaoping. 1-6 [doi]
• Activity Estimation for Field-Programmable Gate ArraysJulien Lamoureux, Steven J. E. Wilton. 1-8 [doi]
• Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement InformationOliver Pell, Wayne Luk. 1-6 [doi]
• Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-ChipBalasubramanian Sethuraman. 1-2 [doi]
• High Performance Scientific Computing Using FPGAs with IEEE Floating Point and Logarithmic Arithmetic for Lattice QCDOwen Callanan, David Gregg, Andy Nisbet, Mike Peardon. 1-6 [doi]
• FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation ApproachKieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Leong. 1-6 [doi]
• Dynamic Memory Sub-System for Reconfigurable PlatformsSu-Shin Ang, George A. Constantinides. 1-2 [doi]
• On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC ChipsHeikki Kariniemi, Jari Nurmi. 1-6 [doi]
• System Level Architecture Exploration for Reconfigurable Systems On ChipKonstantinos Masselos, Kari Tiensyrjä, Yang Qu, Nikos S. Voros, Miroslav Cupák, Luc Rijnders, Marko Pettissalo. 1-6 [doi]
• Skin Color Detection for Real Time Mobile ApplicationsF. Javier Toledo, José-Javier Martínez, F. Javier Garrigós, José M. Ferrández, V. Rodellar. 1-4 [doi]
• A Thermal Management and Profiling Method for Reconfigurable Hardware ApplicationsPhillip H. Jones, John W. Lockwood, Young H. Cho. 1-7 [doi]
• Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAsPatrick Lysaght, Brandon Blodget, Jeff Mason, Jay Young, Brendan Bridgford. 1-6 [doi]
• Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing ToolsDavid Grant, Scott Chin, Guy G. Lemieux. 1-4 [doi]
• Execution Objects for Dynamically Reconfigurable FPGA SystemsTimothy F. Oliver, Douglas L. Maskell. 1-4 [doi]
• From Equation to VHDL: Using Rewriting Logic for Automated Function GenerationCarlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein. 1-4 [doi]
• Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable HardwareArfan Ghani, T. Martin McGinnity, Liam P. Maguire, Jim Harkin. 1-2 [doi]
• Multitasking Support for Dynamically Reconfig Urable SystemsHeiko Hinkelmann, Andreas Gunberg, Peter Zipf, Leandro Soares Indrusiak, Manfred Glesner. 1-6 [doi]
• Investigating Trace Transform Architectures for Face AuthenticationSuhaib A. Fahmy. 1-2 [doi]
• The Entropy of FPGA ReconfigurationUsama Malik, Oliver Diessel. 1-6 [doi]
• An Implementation Technique of Multi-Cycled Arithmetic Functions For a Dynamically Reconfigurable ProcessorMiwa Miyata, Hideyuki Tsuchiya, Yuichiro Shibata, Kiyoshi Oguri. 1-4 [doi]
• An Alternative to Sequential Architectures to Improve the Processing Time of Passive Stereovision AlgorithmsAbdelelah Naoulou, Jean-Louis Boizard, Jean-Yves Fourniols, Michel Devy. 1-4 [doi]
• Ray Tracing Hardware System Using Plane-Sphere IntersectionsYoshiyuki Kaeriyama, Daichi Zaitsu, Kazuhiko Komatsu, Ken-ichi Suzuki, Tadao Nakamura, Nobuyuki Ohba. 1-6 [doi]
• Improved Interpolation and System Integration for FPGA-Based Molecular Dynamics SimulationsYongfeng Gu, Tom Van Court, Martin C. Herbordt. 1-8 [doi]
• Reducing the Space Complexity of Pipelined Routing Using Modified Range EncodingAllan Carroll, Carl Ebeling. 1-6 [doi]
• An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical SystemsMasato Yoshimi, Yasunori Osana, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano. 1-6 [doi]
• Executing Hardware as Parallel Software for Picoblaze NetworksPengyuan Yu, Patrick Schaumont. 1-6 [doi]
• Identifying FPGA IP-Cores Based on Lookup Table Content AnalysisDaniel Ziener, Stefan Assmus, Jürgen Teich. 1-6 [doi]
• Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW CodesignMarco D. Santambrogio, Donatella Sciuto. 1-2 [doi]
• An FPGA-Based System on Chip for the Measurement of QCM Sensors ResolutionMaría José Moure, María Dolores Valdés, Pablo Rodiz, Loreto Rodríguez-Pardo, José Fariña. 1-4 [doi]
• OSSS+R: Modelling and Simulating Self-Reconfigurable SystemsAndreas Schallenberg, Wolfgang Nebel, Frank Oppenheimer. 1-6 [doi]
• Wire Segment Length and Switch Box Co-Optimization for FPGA ArchitecturesKostas Siozios, Dimitrios Soudris. 1-4 [doi]
• Integrating the Electronics of the Control-Loops of the JPL/Boeing Gyroscope Within an Evolvable Hardware ArchitectureEvangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson. 1-4 [doi]
• Astra: An Advanced Space-Time Reconfigurable ArchitectureAlexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki. 1-4 [doi]
• High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAsGabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz. 1-4 [doi]
• High-Level Power Optimization for Digital Signal Processing in Reconfigurable LogicJonathan A. Clarke, George A. Constantinides. 1-2 [doi]
• Adaptive Optics Real-Time Control Using FPGALuis F. Rodriguez-Ramos, Angel Alonso, Fernando Gago, Jose V. Gigante, Guillermo Herrera, Teodora Viera. 1-6 [doi]
• Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source DescriptionLee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann, Oliver Pell. 1-6 [doi]
• Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSipYasunori Osana, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano. 1-6 [doi]
• A Method of Generating Highly Efficient String Matching Circuit for Intrusion DetectionToshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi. 1-4 [doi]
• Intelligent Parking System Design Using FPGAKeith Gowan, Jason Nery, Henrick Han, Tony Sheng, Howard Li, Fakhreddine Karray, Insop Song. 1-6 [doi]
• FPGA Implementation of High-Performance PHM / DPHM SchedulersEnrique Soto, Elena Lago, Juan J. Rodríguez-Andina. 1-4 [doi]
• High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA ArchitecturesRafael A. Arce-Nazario, Manuel Jiménez, Domingo Rodríguez. 1-4 [doi]
• A Framework for a Dynamically Reconfigurable System in a Parallel Multi-Tasking EnvironmentPil Woo Chun, Lev Kirischian. 1-2 [doi]
• Micro-Coded Datapaths: Populating the Space Between Finite State Machine and ProcessorChidamber Kulkarni, Gordon J. Brebner. 1-6 [doi]
• FPGA Implementation of a Ridge Extraction Fingerprint Algorithm Based on Microblaze and Hardware CoprocessorMariano Lopez Garcia, Enrique F. Canto Navarro. 1-5 [doi]
• Evaluation and Design of Processor-Like Reconfigurable ArchitecturesTobias Oppold. 1-2 [doi]
• Implementation of a Parallel and Pipelined Watershed Algorithm on FPGADang Ba Khac Trieu, Tsutomu Maruyama. 1-6 [doi]
• Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling SystemSutjipto Arifin, Peter Y. K. Cheung. 1-4 [doi]
• A Novel FPGA Design Acceleration Methodology Supported by a Unique RP Platform for Fast and Easy System DevelpomentCarsten Bieser. 1-2 [doi]
• A Layer Model for Systematically Designing Dynamically Reconfigurable SystemsBoris Kettelhoit, Mario Porrmann. 1-6 [doi]
• Archlog: High-Level Synthesis of Reconfigurable Multiprocessors for Logic ProgrammingAndreas Fidjeland, Wayne Luk. 1-6 [doi]
• FPGA Architecture Design MethodologyMike Hutton. 1 [doi]
• Hthreads: A Computational Model for Reconfigurable DevicesWesley Peck, Erik Anderson, Jason Agron, Jim Stevens, Fabrice Baijot, David L. Andrews. 1-4 [doi]
• A Flexible Implementation of a Temporal Filter with Motion CompensationThomas Perschke. 1-4 [doi]
• High Speed High Fidelity Infrared Scene Simulation Using Reconfigurable ComputingVinay Sriram, David Kearney. 1-2 [doi]
• Placement and Timing for FPGAs Considering VariationsMike Hutton, Yan Lin, Lei He. 1-7 [doi]
• FPGA Design Considerations in the Implementation of a Fixed-Throughput Sphere Decoder for MIMO SystemsLuis G. Barbero, John S. Thompson. 1-6 [doi]
• FPGAs at 65NM and Beyond - Powerful New FPGAs Bring New ChallengesKen McElvain. 1 [doi]
• Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable ArraysFlorian Stock, Andreas Koch. 1-6 [doi]
• A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System SetupCarsten Bieser, Martin Bahlinger, Matthias Heinz, Christian Stops, Klaus D. Müller-Glaser. 1-4 [doi]
• A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable ProcessorsHideharu Amano, Yohei Hasegawa, Shohei Abe, K. Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, Takuro Nakamura, Takashi Nishimura. 1-6 [doi]
• On Reconfigurable Architectures for Efficient Matrix InversionGoncalo M. de Matos, Horácio C. Neto. 1-6 [doi]
• A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC CodesPaul Saunders, Anthony D. Fagan. 1-6 [doi]
• A Dynamically Reconfigurable Queue SchedulerChristoforos Kachris, Stamatis Vassiliadis. 1-4 [doi]
• Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation AlgorithmKonstantinos Masselos, George A. Constantinides, Qiang Liu. 1-6 [doi]
• Synthesis of Analog Filters on a Continuous-Time FPAA Using a Genetic AlgorithmJoachim Becker, Yiannos Manoli. 1-4 [doi]
• Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-ChipBalasubramanian Sethuraman, Ranga Vemuri. 1-4 [doi]
• Development of IP Modules of Fuzzy Controllers for the Design of Embedded Systems on FPGAsMaría Brox, Santiago Sánchez-Solano. 1-2 [doi]
• An FPGA-Based Dynamically Reconfigurable Platform: From Concept to RealizationMateusz Majer. 1-2 [doi]
• Applying Partial Reconfiguration to Networks-On-ChipsThilo Pionteck, Roman Koch, Carsten Albrecht. 1-6 [doi]
• Pre-Synthesis Area Estimation of Reconfigurable Streaming AcceleratorsSomsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas. 1-4 [doi]
• Predictive Load Balancing for Interconnected FPGAsJason D. Bakos, Charles L. Cathey, Allen Michalski. 1-4 [doi]
• Variable-Length Hashing for Exact Pattern MatchingDionisios N. Pnevmatikatos, Aggelos Arelakis. 1-6 [doi]
• Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable ArchitecturesJanina A. Brenner, Jan van der Veen, Sándor P. Fekete, Julio A. de Oliveira Filho, Wolfgang Rosenstiel. 1-6 [doi]
• FPGA Vendor Agnostic True Random Number GeneratorDries Schellekens, Bart Preneel, Ingrid Verbauwhede. 1-6 [doi]
• Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable ArchitectureSujan Pandey, Manfred Glesner. 1-6 [doi]
• Power Implications of Implementing Logic Using FPGA Embedded Memory ArraysScott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton. 1-8 [doi]
• Efficient Cell Designs for Systolic Smith-Waterman ImplementationsMustafa Gök, Çaglar Yilmaz. 1-4 [doi]
• Can Graphics Processing Units be Used to Improve Video Processing Systems?Ben Cope. 1-2 [doi]
• Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO ReceiverAngel Fernandez Herrero, Alberto Jimenez-Pacheco, Gabriel Caffarena, Javier Casajús-Quirós. 1-4 [doi]
• Minimizing Communication Cost for Reconfigurable Slot ModulesSándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich. 1-6 [doi]
• Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGAJoaquín Olivares, Ignacio Benavides, Javier Hormigo, Julio Villalba, Emilio L. Zapata. 1-4 [doi]
• A Simulation Platform for Reconfigurable Computing ResearchWenyin Fu, Katherine Compton. 1-7 [doi]
• A Congestion Driven Placement Algorithm for FPGA SynthesisYue Zhuo, Hao Li, Saraju P. Mohanty. 1-4 [doi]
• FPGA Design of A H.264/AVC Main Profile Decoder for HDTVLuciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana Gadelha Serra dos Santos, Sergio Bampi, Altamiro Amadeu Susin. 1-6 [doi]
• A Compiler Intermediate Representation for Reconfigurable FabricsZhi Guo, Walid A. Najjar. 1-4 [doi]
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