Tatiana Gadelha Serra dos Santos - researchr alias

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Viewing Publication 1 - 9 from 9

2009

FPGA implementation and performance evaluation of an RFC 2544 compliant Ethernet test setCristiano Bonato Both, Cristiano Battisti, Felipe A. Kuentzer, Tatiana Gadelha Serra dos Santos, Rafael R. dos Santos. ijhpsa, 2(2):107-115, 2009. [doi]

2007

High Level RTOS Scheduler Modeling for a Fast Design ValidationFabiano Hessel, César A. M. Marcon, Tatiana Gadelha Serra dos Santos. isvlsi 2007: 461-466 [doi]

2006

FPGA Design of A H.264/AVC Main Profile Decoder for HDTVLuciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana Gadelha Serra dos Santos, Sergio Bampi, Altamiro Amadeu Susin. fpl 2006: 1-6 [doi]

Scheduling refinement in abstract RTOS modelsFabiano Hessel, Vitor M. da Rosa, Carlos Eduardo Reif, César A. M. Marcon, Tatiana Gadelha Serra dos Santos. tecs, 5(2):342-354, 2006. [doi]

2005

Reusing Traces in a Dynamic Conditional Execution ArchitectureTatiana Gadelha Serra dos Santos, Sergio Bampi, Philippe Olivier Alexandre Navaux. sbac-pad 2005: 126-133 [doi]

2004

Reusing values in a dynamic conditional execution architectureTatiana Gadelha Serra dos Santos. PhD thesis, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil, 2004. [doi]

2003

Complex Branch Profiling for Dynamic Conditional ExecutionRafael R. dos Santos, Tatiana Gadelha Serra dos Santos, Maurício L. Pilla, Philippe Olivier Alexandre Navaux, Sergio Bampi, Mario Nemirovsky. sbac-pad 2003: 28-35 [doi]

2001

Evaluating the Effects of Branch Prediction Accuracy on the Performance of SMT ArchitecturesRonaldo GonÃ§alves, MaurÃcio L. Pilla, Guilherme Dal Pizzol, Tatiana Gadelha Serra dos Santos, Philippe Olivier Alexandre Navaux, Rafael Santos. pdp 2001: 355-362 [doi]

2000

Analyzing Instruction Prefetch Schemes in Superscalar ArchitecturesTatiana Gadelha Serra dos Santos, Sergio Bampi. pdpta 2000:

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