Carsten Bieser - researchr alias

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Viewing Publication 1 - 7 from 7

2007

Konzept einer bibliotheksbasiert konfigurierbaren Hardware-Testeinrichtung für eingebettete elektronische SystemeCarsten Bieser. PhD thesis, Karlsruhe Institute of Technology, 2007. [doi]

2006

A Novel FPGA Design Acceleration Methodology Supported by a Unique RP Platform for Fast and Easy System DevelpomentCarsten Bieser. fpl 2006: 1-2 [doi]

Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAsCarsten Bieser, Klaus D. Müller-Glaser. rsp 2006: 193-199 [doi]

A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System SetupCarsten Bieser, Martin Bahlinger, Matthias Heinz, Christian Stops, Klaus D. Müller-Glaser. fpl 2006: 1-4 [doi]

2005

Hardware/Software Co-Training Lab: From VHDL Bit-Level Coding up to CASE-Tool Based System ModelingCarsten Bieser, Klaus D. Müller-Glaser, Jürgen Becker. mse 2005: 51-52 [doi]

COMPASS - A Novel Concept of a Reconfigurable Platform for Automotive System Development and TestCarsten Bieser, Klaus D. Müller-Glaser. rsp 2005: 135-140 [doi]

2003

Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-CoreJens E. Becker, Carsten Bieser, Alexander Thomas, Klaus D. Müller-Glaser, Jürgen Becker. mse 2003: 134-135 [doi]

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