Abstract is missing.
- Message from the Organizing Chair [doi]
- Message from the Program Chairs [doi]
- Message from the General Chairs [doi]
- Conference Committees [doi]
- Synthesis of Communication Structures and Protocols in Distributed Embedded SystemsStefan Ihmor, Tobias Loke, Wolfram Hardt. 3-9 [doi]
- Heterogeneous Modelling of an Optical Network-on-Chip with SystemCMatthieu Briere, Emmanuel Drouard, Fabien Mieyeville, David Navarro, Ian O Connor, Frédéric Gaffiot. 10-16 [doi]
- Models for Embedded Application Mapping onto NoCs: Timing AnalysisCésar A. M. Marcon, Márcio Eduardo Kreutz, Altamiro Amadeu Susin, Ney Laert Vilar Calazans. 17-23 [doi]
- Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2R. Lemaire, Fabien Clermidy, Y. Durand, D. Lattard, Ahmed Amine Jerraya. 24-30 [doi]
- Leveraging Model Representations for System Level Design ToolsJames Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu. 33-39 [doi]
- Porting DSP Applications across Design Tools Using the Dataflow Interchange FormatChia-Jui Hsu, Shuvra S. Bhattacharyya. 40-46 [doi]
- Automatic Generation of Component Wrappers by Composition of Hardware Library Elements Starting from Communication Service SpecificationArnaud Grasset, Frédéric Rousseau, Ahmed Amine Jerraya. 47-53 [doi]
- High Level Synthesis for Data-Driven ApplicationsEtienne Bergeron, Xavier Saint-Mleux, Marc Feeley, Jean-Pierre David. 54-60 [doi]
- Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAsMehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi. 63-69 [doi]
- Dynamic Reconfiguration of IP-Based SystemsMarkus Visarius, André Meisel, Markus Scheithauer, Wolfram Hardt. 70-76 [doi]
- Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAsYana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo. 77-83 [doi]
- A Practical Approach for Circuit Routing on Dynamic Reconfigurable DevicesAli Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen. 84-90 [doi]
- Simulation of Resolution of CS Problem for Multiple Common Variables in Multiprocessor EnvironmentGhulam Qader, M. Younus Javed. 93-98 [doi]
- Rapid Prototyping of Embedded Software Using Selective FormalismJohn Carter, Ming Xu, W. B. Gardner. 99-104 [doi]
- Test-Time, Run-Time, and Simulation-Time Temporal Assertions in RSPDoron Drusinsky, Man-tak Shing, Kadir Alpaslan Demir. 105-110 [doi]
- Rapid Development Methodology for Customized MiddlewareThomas Vergnaud, Jérôme Hugues, Laurent Pautet, Fabrice Kordon. 111-117 [doi]
- An 8-GHz Ultra Wideband Transceiver Prototyping TestbedDeepak Argarwal, Christopher Robert Anderson, Peter M. Athanas. 121-127 [doi]
- Enabling a Real-Time Solution for Neuron Detection with Reconfigurable HardwareBen Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel. 128-134 [doi]
- COMPASS - A Novel Concept of a Reconfigurable Platform for Automotive System Development and TestCarsten Bieser, Klaus D. Müller-Glaser. 135-140 [doi]
- Optimization of Memory Allocation for Real-Time Video Processing on FPGABenny Thörnberg, Leif Olsson, Mattias O Nils. 141-147 [doi]
- Custom Instruction Filter Cache Synthesis for Low-Power Embedded SystemsKugan Vivekanandarajah, Thambipillai Srikanthan. 151-157 [doi]
- Performance Improvement of Multiprocessor Simulation by Optimizing Synchronization a CommunicationMoo-Kyoung Chung, Heejun Shim, Chong-Min Kyung. 158-164 [doi]
- Optimization Techniques for ADL-Driven RTL Processor SynthesisOliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr. 165-171 [doi]
- Automated Floating-Point to Fixed-Point Conversion with the Fixify EnvironmentPavle Belanovic, Markus Rupp. 172-178 [doi]
- Discrete-Continuous Simulation Model for Accurate Validation in Component-Based Heterogeneous SoC DesignFaouzi Bouchhima, Gabriela Nicolescu, El Mostapha Aboulhamid, Mohamed Abid. 181-187 [doi]
- Test Automation and Safety Assessment in Rapid Systems PrototypingMikhail Auguston, James Bret Michael, Man-tak Shing. 188-194 [doi]
- A Test Language for CO-OPN SpecificationsLevi Lucio, Luis Pedro, Didier Buchs. 195-201 [doi]
- On the Use of Rewriting Logic for Verification of Distributed Software Architecture Description Based LfPChadlia Jerad, Kamel Barkaoui. 202-208 [doi]
- The Ordering of Events in a Prototyping PlatformSilvio Dragone, Clemens Lombriser. 211-217 [doi]
- Systematic Design Flow for Fast Hardware/Software Prototype Generation from Bus Functional Model for MPSoCIvan Petkov, Paul Amblard, Marin Hristov. 218-224 [doi]
- Modeling and Prototyping of Communication Systems Using Java: A Case StudyLeandro Soares Indrusiak, Romualdo Begale Prudencio, Manfred Glesner. 225-231 [doi]
- A Rapid System Prototyping Platform for Error Control Coding in Optical CDMA NetworksMartin Irman, Jan Bajcsy. 232-234 [doi]
- A C/C++-Based Functional Verification Framework Using the SystemC Verification LibrarySanggyu Park, Soo-Ik Chae. 237-239 [doi]
- Design Exploration and HW/SW Rapid Prototyping for Real-Time System DesignSylvain Huet, Emmanuel Casseau, Olivier Pasquier. 240-243 [doi]
- An Approach for Functional Decomposition Applied to State-Based DesignsLuke Demoracski, Dimiter R. Avresky. 243-245 [doi]
- Communication Primitives Driven Hardware Design and Test Methodology Applied on Complex Video ApplicationsAdrian Chirila-Rus, Kristof Denolf, Bart Vanhoof, Paul R. Schumacher, Kees A. Vissers. 246-249 [doi]
- Thread-Level Parallel Execution in Co-Designed Virtual MachinesThomas S. Hall, Kenneth B. Kent. 249-251 [doi]
- Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW UnitsArnaldo Azevedo, Luciano Volcan Agostini, Flávio Rech Wagner, Sergio Bampi. 255-257 [doi]
- SyCE: An Integrated Environment for System Design in SystemCRolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große. 258-260 [doi]
- KoVer: A Sophisticated Residue Arithmetic Core GeneratorNikolaos Kostaras, Haridimos T. Vergos. 261-263 [doi]
- A HyperTransport Chip-to-Chip Interconnect Tunnel Developed Using SystemCAmi Castonguay, Yvon Savaria. 264-266 [doi]
- Prototyping a Residential Gateway Using Xilinx ISES. W. Song, J. D. Zheng, W. B. Gardner. 267-269 [doi]