Abstract is missing.
- How Can the Earth Simulator Impact on Human ActivitiesTetsuya Sato, Hitoshi Murai, Shigemune Kitawaki. 1-7 [doi]
- Toward Architecting and Designing Novel ComputersTadao Nakamura. 8-13 [doi]
- Designing Ultra-large Instruction Issue WindowsDoug Burger. 14-20 [doi]
- Multi-threaded Microprocessors - Evolution or RevolutionChris R. Jesshope. 21-45 [doi]
- The Development of System Software for Parallel SupercomputersVictor Korneev. 46-53 [doi]
- Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCAKiyoshi Oguri, Yuichiro Shibata, Akira Nagoya. 54-68 [doi]
- Reconfigurable Logic: A Saviour for Experimental Computer Architecture ResearchJohn Morris. 69-85 [doi]
- Design and Implementation of Java ProcessorsAmos Omondi. 86-96 [doi]
- MOOSS: CPU Architecture with Memory Protection and Support for OOPRadim Ballner, Pavel Tvrdík. 97-111 [doi]
- Reducing Access Count to Register-Files through Operand ReuseHiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga. 112-121 [doi]
- SimAlpha Version 1.0: Simple and Readable Alpha Processor SimulatorKenji Kise, Hiroki Honda, Toshitsugu Yuba. 122-136 [doi]
- Towards an Asynchronous MIPS ProcessorQianyi Zhang, Georgios K. Theodoropoulos. 137-150 [doi]
- On Implementing High Level Concurrency in JavaG. Stewart Von Itzstein, Mark Jasiunas. 151-165 [doi]
- Simultaneous MultiStreaming for Complexity-Effective VLIW ArchitecturesPradeep Rao, S. K. Nandy, M. N. V. Satya Kiran. 166-179 [doi]
- A Novel Architecture for Genomic Sequence Searching and AlignmentPaul Gardner-Stephen, Greg Knowles. 180-192 [doi]
- A Reconfigurable Multi-threaded Architecture ModelSebastian Wallner. 193-207 [doi]
- Reconfigurable Instruction-Level Parallel Processor ArchitectureToshiyuki Ito, Kentaro Ono, Mayumi Ichikawa, Yuichi Okuyama, Kenichi Kuroda. 208-220 [doi]
- Mapping Applications to a Coarse Grain Reconfigurable SystemYuanqing Guo, Gerard J. M. Smit, Hajo Broersma, Michèl A. J. Rosien, Paul M. Heysters. 221-235 [doi]
- Packing with Boundary Constraints for a Reconfigurable Operating SystemAbhinandan Sharma, Martyn A. George, David A. Kearney. 236-245 [doi]
- Arithmetic Circuits Combining Residue and Signed-Digit RepresentationsAnders Lindström, Michael Nordseth, Lars Bengtsson, Amos Omondi. 246-257 [doi]
- A New On-the-fly Summation AlgorithmHooman Nikmehr, Cheng-Chew Lim. 258-267 [doi]
- State Reordering for Low Power Combinational LogicKun-Lin Tsai, Feipei Lai, Shanq-Jang Ruan, Szu-Wei Chaung. 268-276 [doi]
- User-Level Management of Kernel MemoryAndreas Haeberlen, Kevin Elphinstone. 277-289 [doi]
- Variable Radix Page Table: A Page Table for Modern ArchitecturesCristan Szmajda, Gernot Heiser. 290-304 [doi]
- L1 Cache and TLB Enhancements to the RAMpage Memory HierarchyPhilip Machanick, Zunaid Patel. 305-319 [doi]
- Legba: Fast Hardware Support for Fine-Grained ProtectionAdam Wiggins, Simon Winwood, Harvey Tuch, Gernot Heiser. 320-336 [doi]
- Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache SubsystemMohan G. Kabadi, Ranjani Parthasarathi. 337-351 [doi]
- Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM ProcessorAdam Wiggins, Harvey Tuch, Volkmar Uhlig, Gernot Heiser. 352-364 [doi]
- Performance of the Achilles RouterSonny Tham, John Morris. 365-379 [doi]
- Latency Improvement in Virtual MulticastingPhilip Machanick, Brynn Andrew. 380-394 [doi]
- A Router Architecture to Achieve Link Rate Throughput in Suburban Ad-hoc NetworksMuhammad Mahmudul Islam, Ronald Pose, Carlo Kopp. 395-407 [doi]