Nobuhiro Ide - researchr alias

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Viewing Publication 1 - 7 from 7

2000

2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computingNobuhiro Ide, Masashi Hirano, Yukio Endo, Shin-ichi Yoshioka, Hiroaki Murakami, Atsushi Kunimatsu, Toshinori Sato, Takayuki Kamei, Toyoshi Okada, Masakazu Suzuoki. jssc, 35(7):1025-1033, 2000. [doi]

300MHz design methodology of VU for emotion synthesisTakayuki Kamei, Hideaki Takeda, Yukio Ootaguro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shin ichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato, Hiroaki Murakami, Nobuhiro Ide, Yukio Endo, Akira Aono, Atsushi Kunimatsu. aspdac 2000: 635-640 [doi]

Vector Unit Architecture for Emotion SynthesisAtsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Fujio Ishihara, Haruyuki Tago, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki. micro, 20(2):40-47, 2000. [doi]

1999

1997

A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic CircuitGensoh Matsubara, Nobuhiro Ide. async 1997: 198-209 [doi]

1995

30-ns 55-b Radix 2 Division and Square Root Using a Self-Timed CircuitGensoh Matsubara, Nobuhiro Ide, Haruyuki Tago, Seigo Suzuki, Nobuyuki Goto. arith 1995: 98 [doi]

1993

A 320 MFLOPS CMOS floating-point processing unit for superscalar processorsNobuhiro Ide, Hiroto Fukuhisa, Yoshihisa Kondo, Takeshi Yoshida, Masato Nagamatsu, Junji Mori, Itaru Yamazaki, Kiyoyi Ueno. jssc, 28(3):352-361, March 1993. [doi]

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