Abstract is missing.
- A Result Forwarding Mechanism for Asynchronous Pipelined SystemsD. A. Gilbert, Jim D. Garside. 2-11 [doi]
- Two-Phase Asynchronous Pipeline ControlSam S. Appleton, Shannon V. Morton, Michael J. Liebelt. 12-23 [doi]
- Built-In Self-Testing of MicropipelinesO. A. Petlin, Stephen B. Furber. 22-29 [doi]
- Self-Timed Meshes Are Faster Than SynchronousPeggy B. K. Pang, Mark R. Greenstreet. 30 [doi]
- Delay Insensitive Logic for RSFQ Superconductor TechnologyPriyadarsan Patra, Stanislav Polonsky, Donald S. Fussell. 42-53 [doi]
- On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary LogicRiccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni. 54 [doi]
- Symbolic Techniques for Performance Analysis of Timed Systems Based on Average Time Separation of EventsAiguo Xie, Peter A. Beerel. 64-75 [doi]
- Response Time Properties of Some Asynchronous CircuitsJo C. Ebergen, Robert Berks. 76 [doi]
- Efficient Timing Analysis Algorithms for Timed State Space ExplorationWendy Belluomini, Chris J. Myers. 88-100 [doi]
- Timing Analysis of Extended Burst-Mode CircuitsSupratik Chakraborty, David L. Dill, Kun-Yung Chang, Kenneth Y. Yun. 101-111 [doi]
- More Accurate Polynomial-Time Min-Max Timing SimulationSupratik Chakraborty, David L. Dill. 112 [doi]
- A Quasi Delay-Insensitive Bus Proposal for Asynchronous SystemsPedro A. Molina, Peter Y. K. Cheung. 126-139 [doi]
- The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation SolverKenneth Y. Yun, Ayoob E. Dooply, Julio Arceo, Peter A. Beerel, Vida Vakilotojar. 140 [doi]
- Action Systems in Pipelined Processor DesignJuha Plosila, Kaisa Sere. 156-166 [doi]
- Normal Form in DI-Algebra with RecursionPaul G. Lucassen, Indra Polak, Jan Tijmen Udding. 167-174 [doi]
- Using Metrics for Proof Rules for Recursively Defined Delay-insensitive SpecificationsWillem C. Mallon, Jan Tijmen Udding. 175 [doi]
- Bundled Data Asynchronous Multipliers with Data Dependent Computation TimesDavid A. Kearney, Neil W. Bergmann. 186-197 [doi]
- A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic CircuitGensoh Matsubara, Nobuhiro Ide. 198-209 [doi]
- Speculative Completion for the Design of High-Performance Asynchronous Dynamic AddersSteven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel. 210 [doi]
- Improved State Assignment for Burst Mode Finite State MachinesJ. W. J. M. Rutten, Michel R. C. M. Berkelaar. 228-239 [doi]
- Technology Mapping for Speed-Independent Circuits: Decomposition and ResynthesisAlex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev. 240-253 [doi]
- Partial order based approach to synthesis of speed-independent circuitsAlexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella, Luciano Lavagno. 254 [doi]
- Designing Asynchronous Standby Circuits for a Low-Power PagerJoep L. W. Kessels, Paul Marston. 268-278 [doi]
- A FIFO Ring Performance ExperimentCharles E. Molnar, Ian W. Jones, William S. Coates, Jon K. Lexau. 279-289 [doi]
- AMULET2e: An Asynchronous Embedded ControllerStephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, P. Day, N. C. Paver. 290 [doi]