Hirofumi Sakamoto, Ken ichiro Uda, Bu-Y. Lee, Hiroyuki Ochi, Kazuo Taki, Takao Tsuda. A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL. In Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan. pages 33-34, ACM, 2000. [doi]
Abstract is missing.