A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Hirofumi Sakamoto, Ken ichiro Uda, Bu-Y. Lee, Hiroyuki Ochi, Kazuo Taki, Takao Tsuda. A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL. In Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan. pages 33-34, ACM, 2000. [doi]

This author has not been identified. Look up 'Hirofumi Sakamoto' in GoogleThis author has not been identified. Look up 'Ken ichiro Uda' in GoogleThis author has not been identified. Look up 'Bu-Y. Lee' in GoogleThis author has not been identified. Look up 'Hiroyuki Ochi' in GoogleThis author has not been identified. Look up 'Kazuo Taki' in GoogleThis author has not been identified. Look up 'Takao Tsuda' in Google

runs on WebDSL