Hirofumi Sakamoto, Ken ichiro Uda, Bu-Y. Lee, Hiroyuki Ochi, Kazuo Taki, Takao Tsuda. A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL. In Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan. pages 33-34, ACM, 2000. [doi]
@inproceedings{SakamotoULOTT00,
title = {A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL},
author = {Hirofumi Sakamoto and Ken ichiro Uda and Bu-Y. Lee and Hiroyuki Ochi and Kazuo Taki and Takao Tsuda},
year = {2000},
doi = {10.1145/368434.368495},
url = {http://doi.acm.org/10.1145/368434.368495},
tags = {logic},
researchr = {https://researchr.org/publication/SakamotoULOTT00},
cites = {0},
citedby = {0},
pages = {33-34},
booktitle = {Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan},
publisher = {ACM},
isbn = {0-7803-5974-7},
}