Abstract is missing.
- Message from the Symposium Chairs [doi]
- Organizing Committee [doi]
- Message from the Program Chair [doi]
- List of Reviewers [doi]
- Design Methods for Multiple-Valued Input Address GeneratorsTsutomu Sasao. 1 [doi]
- Algorithm-level interpretation of fast adder structures in binary and multiple-valued logicNaofumi Homma, Takafumi Aoki, Tatsuo Higuchi. 2 [doi]
- On Designs of Radix Converters Using Arithmetic DecompositionsYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. 3 [doi]
- New Data Encoding Method with a Multi-Value Logic for Low Power Asynchronous Circuit DesignEun-Ju Choi, Kyoung-Rok Cho, Je-Hoon Lee. 4 [doi]
- Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential LogicAkira Mochizuki, Takahiro Hanyu. 5 [doi]
- Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip ArchitectureHaque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama. 6 [doi]
- On the Ranges of Algebraic Functions in Lattices - A Preliminary ReportSergiu Rudeanu, Dan A. Simovici. 7 [doi]
- Upper and Lower Bounds on the Number of Disjunctive FormsHisayuki Tatsumi, Masahiro Miyakawa, Masao Mukaidono. 8 [doi]
- Completeness of a Hypersequent Calculus for Some First-order Godel Logics with DeltaMatthias Baaz, Norbert Preining, Richard Zach. 9 [doi]
- Assumption based multi-valued semantics for extended logic programsDaniel Stamate. 10 [doi]
- Implementation of Multiple-Valued CAM Functions by LUT CascadesTsutomu Sasao, Jon T. Butler. 11 [doi]
- The new architecture of radix-4 Chinese abacus adderShu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin, Chuen-Ching Wang, Chin-Fa Hsieh, Chih-Yung Lu. 12 [doi]
- Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair CircuitHaque Mohammad Munirul, Michitaka Kameyama. 13 [doi]
- Design of a Microprocessor Datapath Using Four-Valued Differential-Pair CircuitsAkira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu. 14 [doi]
- A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistorslos Roberto Mingoto Jr.. 15 [doi]
- Signal Processing Algorithms and Multiple-Valued Logic Design MethodsJaakko Astola, Radomir S. Stankovic. 16 [doi]
- Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching SignalsYoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama. 17 [doi]
- A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate DevicesHenning Gundersen, Yngvar Berg. 18 [doi]
- A High-Density Ternary Content-Addressable Memory Using Single-Electron TransistorsKatsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi. 19 [doi]
- A Feedback-Signal Shaping Technique for Multi-Level Continuous-Time Delta-Sigma Modulators with Clock-JitterMitsuhiro Tanihata, Takao Waho. 20 [doi]
- Commuting HyperoperationsJovanka Pantovic, Gradimir Vojvodic. 21 [doi]
- Theoretical Basis of Commutation Theory for Partial ClonesLucien Haddad, Hajime Machida, Ivo G. Rosenberg. 22 [doi]
- Associativity Test in HypergroupoidsMasahiro Miyakawa, Ivo G. Rosenberg, Hisayuki Tatsumi. 23 [doi]
- Some Observations on Minimal ClonesHajime Machida, Michael Pinsker. 24 [doi]
- Efficiency of Multi-Valued Encoding in SAT-based ATPGGörschwin Fey, Junhao Shi, Rolf Drechsler. 25 [doi]
- Towards Solving Many-Valued MaxSATJosep Argelich, Xavier Domingo, Chu Min Li, Felip Manyà, Jordi Planes. 26 [doi]
- Random Multiple-Valued Networks: Theory and ApplicationsElena Dubrova. 27 [doi]
- Representations of Elementary Functions Using Binary Moment DiagramsTsutomu Sasao, Shinobu Nagayama. 28 [doi]
- Embedding and Assembling Techniques for Spatial Computing Structure Design using Decision Trees and DiagramsSvetlana N. Yanushkevich, Vlad P. Shmerko, Oleg Boulanov. 29 [doi]
- QMDD: A Decision Diagram Structure for Reversible and Quantum CircuitsD. Michael Miller, Mitchell A. Thornton. 30 [doi]
- Arithmetic-Haar Spectral Transform Decision DiagramsBogdan J. Falkowski, Shixing Yan. 31 [doi]
- Multi-Valued Quantum LogicMichael Katz. 32 [doi]
- A Quantum CAD Accelerator Based on Grover s Algorithm for Finding the Minimum Fixed Polarity Reed-Muller FormLun Li, Mitchell A. Thornton, Marek A. Perkowski. 33 [doi]
- Generation and Relation of Quaternary and Binary Linearly Independent TransformsBogdan J. Falkowski, Cheng Fu. 34 [doi]
- Properties of matrix-valued spectral coefficients obtained with the Fourier Transform on a non-Abelian groupClaudio Moraga, Radomir S. Stankovic, Jaakko Astola. 35 [doi]