Hiroshi Inokawa - researchr alias

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Viewing Publication 1 - 19 from 19

2024

Multiple Quantum Barrier Avalanche Photodiode Based on GaN/AlGaN Heterostructures for Long Wavelength Infrared DetectionSomrita Ghosh, Aritra Acharyya, Arindam Biswas 0007, Amit Banerjee, Hiroshi Inokawa, Hiroaki Satoh, Alexey Y. Seteikin, I. G. Samusev. access, 12:16022-16038, 2024. [doi]

2023

Folded-Dipole Antenna Geometrical Analysis for THz MicrobolometerArie Pangesti Aji, Hiroaki Satoh, Catur Apriono, Eko Tjipto Rahardjo, Hiroshi Inokawa. access, 11:25713-25722, 2023. [doi]

Refractive Index Measurement Using SOI Photodiode with SP Antenna toward SOI CMOS-Compatible Integrated Optical BiosensorHiroaki Satoh, Koki Isogai, Shohei Iwata, Taiki Aso, Ryosuke Hayashi, Shu Takeuchi, Hiroshi Inokawa. sensors, 23(2):568, January 2023. [doi]

2022

Responsivity and NEP Improvement of Terahertz Microbolometer by High-Impedance AntennaArie Pangesti Aji, Hiroaki Satoh, Catur Apriono, Eko Tjipto Rahardjo, Hiroshi Inokawa. sensors, 22(14):5107, 2022. [doi]

Angle-sensitive pixel based on silicon-on-insulator p-n junction photodiode with aluminum grating gate electrodeHiroaki Satoh, Ken Kawakubo, Atsushi Ono, Hiroshi Inokawa. ieiceee, 19(21):20220428, 2022. [doi]

2020

Angular selectivity of SOI photodiode with surface plasmon antennaAnitharaj Nagarajan, Shusuke Hara, Hiroaki Satoh, Aruna Priya Panchanathan, Hiroshi Inokawa. ieiceee, 17(13):20200187, 2020. [doi]

Angle-Sensitive Detector Based on Silicon-On-Insulator Photodiode Stacked with Surface Plasmon AntennaAnitharaj Nagarajan, Shusuke Hara, Hiroaki Satoh, Aruna Priya Panchanathan, Hiroshi Inokawa. sensors, 20(19):5543, 2020. [doi]

2018

Application of bow-tie surface plasmon antenna to silicon on insulator nanowire photodiode for enhanced light absorptionYash Sharma, Hiroaki Satoh, Hiroshi Inokawa. ieiceee, 15(11):20180328, 2018. [doi]

2016

Evaluation of multidrug cancer chronotherapy based on cell cycle model under influences of circadian clockHiroshi Inokawa, Norihiro Katayama, Mitsuyuki Nakao. embc 2016: 1439-1442 [doi]

2012

Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array DeviceMingu Jo, Yuki Kato, Masashi Arita, Yukinori Ono, Akira Fujiwara, Hiroshi Inokawa, Yasuo Takahashi, Jung-Bum Choi. ieicet, 95-C(5):865-870, 2012. [doi]

2009

Full Adder Operation Based on Si Nanodot Array Device with Multiple Inputs and OutputsTakuya Kaizawa, Mingyu Jo, Masashi Arita, Akira Fujiwara, Kenji Yamazaki, Yukinori Ono, Hiroshi Inokawa, Yasuo Takahashi. ijnmc, 1(2):58-69, 2009. [doi]

2007

Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron TransistorsKatsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi. mvl, 13(3):249-266, 2007. [doi]

Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect TransistorsWancheng Zhang, Katsuhiko Nishiguchi, Yukinori Ono, Akira Fujiwara, Hiroshi Yamaguchi, Hiroshi Inokawa, Yasuo Takahashi, Nan-Jian Wu. ieicet, 90-C(5):943-948, 2007. [doi]

2006

A High-Density Ternary Content-Addressable Memory Using Single-Electron TransistorsKatsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi. ismvl 2006: 19 [doi]

2005

A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron TransistorsKatsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi. ismvl 2005: 32-38 [doi]

2004

A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode LogicKatsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi. ismvl 2004: 262-268 [doi]

A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch FunctionsHiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi. ismvl 2004: 269-274 [doi]

2003

Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued LogicHiroshi Inokawa, Yasuo Takahashi. ismvl 2003: 259-266 [doi]

1997

A 0.5-V MTCMOS/SIMOX logic gateTakakuni Douseki, Satoshi Shigematsu, Junzo Yamada, Mitsuru Harada, Hiroshi Inokawa, Toshiaki Tsuchiya. jssc, 32(10):1604-1609, 1997. [doi]

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