Abstract is missing.
- Two New Awards [doi]
- List of Reviewers [doi]
- Organizing Committee [doi]
- Message from the Program Chair [doi]
- Message from the Symposium Chairs [doi]
- Classical vs Quantum FingerprintingBarry C. Sanders. 2-5 [doi]
- An Abstract Axiomatization of the Notion of EntropyIvo G. Rosenberg, Dan A. Simovici. 8-13 [doi]
- On Prior s Three-Valued Modal Logic QSeiki Akama, Yasunori Nagata. 14-19 [doi]
- Polynomial Ring Calculus for Many-Valued LogicsWalter Alexandre Carnielli. 20-25 [doi]
- Partially Ordered Set with Residuated t-normMichiro Kondo, Mayuka F. Kawaguchi. 26-29 [doi]
- A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron TransistorsKatsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi. 32-38 [doi]
- Multi-Valued DNA-Based Electronic NanodevicesMarina Alexandra Lyshevski. 39-42 [doi]
- A Design of 10-GHz Delta-Sigma Modulator using a 4-Level Differential Resonant-Tunneling QuantizerKeisuke Eguchi, Masaru Chibashi, Takao Waho. 43-47 [doi]
- Multi-Valued Nanoelectronics With FullerenesSergey Edward Lyshevski. 48-53 [doi]
- A Novel Ternary Switching Element Using CMOS Recharge Semi Floating-Gate DevicesHenning Gundersen, Renè Jensen, Yngvar Berg. 54-58 [doi]
- Test Generation and Fault Localization for Quantum CircuitsMarek A. Perkowski, Jacob Biamonte, Martin Lukac. 62-68 [doi]
- Complete Bi-Decomposition of Multiple-Valued Functions Using MIN and MAX GatesBernd Steinbach, Christian Lang. 69-74 [doi]
- Hardware to Compute Walsh CoefficientsYukihiro Iguchi, Tsutomu Sasao. 75-81 [doi]
- Three Dimensional Multi-Valued Design in Nanoscale Integrated CircuitsSergey Edward Lyshevski. 82-87 [doi]
- Multiple-Valued Logic Approach for a Systolic^2 AB Circuit in Galois FieldNabil Abu-Khader, Pepe Siy. 88-93 [doi]
- On the Partial Hyperclone LatticeJovanka Pantovic, Gradimir Vojvodic. 96-100 [doi]
- Partial Clones Determined by Concatenated RelationsLucien Haddad, Ivo G. Rosenberg. 101-106 [doi]
- Semirigid Equivalence Relations - A New Proof MethodMasahiro Miyakawa, Ivo G. Rosenberg, Hisayuki Tatsumi. 107-112 [doi]
- Multiple-Valued VLSI Architecture for Intra-Chip Packet Data TransferTomoaki Hasegawa, Yuya Homma, Michitaka Kameyama. 114-119 [doi]
- Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled LogicHaque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama. 120-125 [doi]
- Multiple-Valued Caches for Power-Efficient Embedded SystemsEmre Özer, Resit Sendag, David Gregg. 126-131 [doi]
- Analog Soft Decoding for Multi-Level MemoriesChris Winstead. 132-137 [doi]
- Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC DecodersNaoya Onizawa, Akira Mochizuki, Takahiro Hanyu. 138-143 [doi]
- Signed-digit CMOS (SD-CMOS) Logic Circuits with Dynamic OperationHideki Fukuda. 144-151 [doi]
- The Alleged Limitations of Fuzzy ControlPhil Serchuk. 154-159 [doi]
- A New Aspect for the Optimization of Fuzzy If-Then RulesClaudio Moraga, Rodrigo Salas. 160-165 [doi]
- Approaching the Physical Limits of ComputingMichael P. Frank. 168-185 [doi]
- Remarks on the Structure of Matrix-Valued Spectral Transforms on Finite Non-Abelian GroupsRadomir S. Stankovic, Claudio Moraga, Jaakko Astola. 188-193 [doi]
- The Karhunen-Loève Transform of Discrete MVL FunctionsMitchell A. Thornton. 194-199 [doi]
- Properties and Relations of Quaternary Linearly Independent Helix TransformationsCheng Fu, Bogdan J. Falkowski. 200-205 [doi]
- Classes of Fastest Quaternary Linearly Independent TransformationsBogdan J. Falkowski, Cheng Fu. 206-211 [doi]
- Many-Valued Intuitionistic Implication and Inference Closure in a Bilattice-Based LogicZoran Majkic. 214-220 [doi]
- A Note on Triangulation of PostAlgebras and Leibnizian LatticesMichel Serfati. 221-226 [doi]
- Centralizers of Monoids Containing the Symmetric GroupHajime Machida, Ivo G. Rosenberg. 227-233 [doi]
- Hahoe KAIST Robot Theatre: Learning Rules of Interactive Robot Behavior as a Multiple-Valued Logic Synthesis ProblemMarek A. Perkowski, Tsutomu Sasao, Jong-Hwan Kim, Martin Lukac, Jeff Allen, Stefan Gebauer. 236-248 [doi]
- Controlling the Memory During Manipulation of Word-Level Decision DiagramsSebastian Kinder, Görschwin Fey, Rolf Drechsler. 250-255 [doi]
- Radix Converters: Complexity and Implementation by LUT CascadesTsutomu Sasao. 256-263 [doi]
- Dynamic Reliability Indices for k-out-of-n Multi-State SystemElena N. Zaitseva, Vitaly G. Levashenko, K. Matiasko, Seppo Puuronen. 264-269 [doi]
- A Characterization of Antisymmetry in Boolean and Multi-Valued FunctionsJacqueline E. Rice, Jon C. Muzio. 270-275 [doi]
- Estimation of Average Multiple-Valued Logic Circuit Size Using Monte Carlo Simulation TechniqueDaniel H. Y. Teng, Ronald J. Bolton. 276-281 [doi]
- Normal Forms for the One-Variable Fragment of Hájek s Basic LogicStefano Aguzzoli, Brunella Gerla. 284-289 [doi]
- Mapping Many-Valued CNF Formulas to Boolean CNF FormulasCarlos Ansótegui, Felip Manyà. 290-295 [doi]
- Quantification in Non-Deterministic Multi-Valued StructuresArnon Avron, Anna Zamansky. 296-301 [doi]