Table of Contents

• First steps towards SAT-based formal analog verificationSaurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips, Claudio Pinello, Radu Zlatanovici. 1-8 [doi]
• Interpolant generation without constructing resolution graphChih-Jen Hsu, Shao-Lun Huang, Chi-An Wu, Chung-Yang Huang. 9-12 [doi]
• A scalable decision procedure for fixed-width bit-vectorsRoberto Bruttomesso, Natasha Sharygina. 13-20 [doi]
• Generation of optimal obstacle-avoiding rectilinear Steiner minimum treeLiang Li, Zaichen Qian, Evangeline F. Y. Young. 21-25 [doi]
• Obstacle-avoiding rectilinear Steiner tree construction based on Steiner point selectionChih-Hung Liu, Shih-Yi Yuan, Sy-Yen Kuo, Jung-Hung Weng. 26-32 [doi]
• How to consider shorts and guarantee yield rate improvement for redundant wire insertionFong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak. 33-38 [doi]
• Power-switch routing for coarse-grain MTCMOS technologiesTsun-Ming Tseng, Mango C.-T. Chao, Chien Pang Lu, Chen Hsing Lo. 39-46 [doi]
• Scheduling with soft constraintsJason Cong, Bin Liu, Zhiru Zhang. 47-54 [doi]
• REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction setMuhammad Shafique, Lars Bauer, Jörg Henkel. 55-62 [doi]
• Enhanced reliability-aware power management through shared recovery techniqueBaoxian Zhao, Hakan Aydin, Dakai Zhu. 63-70 [doi]
• Resilient circuits - Enabling energy-efficient performance and reliabilityJames Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik. 71-73 [doi]
• Resilience in computer systems and networksKishor S. Trivedi, Dong Seong Kim, Rahul Ghosh. 74-77 [doi]
• Scan power reduction in linear test data compression schemeMingjing Chen, Alex Orailoglu. 78-82 [doi]
• Compacting test vector sets via strategic use of implicationsNuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan Nepal. 83-88 [doi]
• Pre-ATPG path selection for near optimal post-ATPG process space coverageJiniun Xionq, Yiyu Shi, Vladimir Zolotov, Chandu Visweswariah. 89-96 [doi]
• A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environmentKohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara. 97-104 [doi]
• IPR: In-Place Reconfiguration for FPGA fault toleranceZhe Feng 0002, Yu Hu, Lei He, Rupak Majumdar. 105-108 [doi]
• A circuit-software co-design approach for improving EDP in reconfigurable frameworksSomnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia. 109-112 [doi]
• Security against hardware Trojan through a novel application of design obfuscationRajat Subhra Chakraborty, Swarup Bhunia. 113-116 [doi]
• MOLES: Malicious off-chip leakage enabled by side-channelsLang Lin, Wayne Burleson, Christof Paar. 117-122 [doi]
• Consistency-based characterization for IC Trojan detectionYousra Alkabani, Farinaz Koushanfar. 123-127 [doi]
• SAT-based protein designNoah Ollikainen, Ellen Sentovich, Carlos Coelho, Andreas Kuehlmann, Tanja Kortemme. 128-135 [doi]
• Synthesizing sequential register-based computation with biochemistryAdam Shea, Marc D. Riedel, Brian Fett, Keshab Parhi. 136-143 [doi]
• An algorithm for identifying dominant-edge metabolic pathwaysEhsan Ullah, Kyongbum Lee, Soha Hassoun. 144-150 [doi]
• A contamination aware droplet routing algorithm for digital microfluidic biochipsTsung-Wei Huang, Chun-Hsien Lin, Tsung-Yi Ho. 151-156 [doi]
• On soft error rate analysis of scaled CMOS designs - A statistical perspectiveHuan-Kai Peng, Charles H.-P. Wen, Jayanta Bhadra. 157-163 [doi]
• Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuningBalaji Vaidyanathan, Anthony S. Oates, Yuan Xie. 164-171 [doi]
• DynaTune: Circuit-level optimization for timing speculation considering dynamic path behaviorLu Wan, Deming Chen. 172-179 [doi]
• A variation-aware preferential design approach for memory based reconfigurable computingSomnath Paul, Saibal Mukhopadhyay, Swarup Bhunia. 180-183 [doi]
• Pre-bond testable low-power clock tree design for 3D stacked ICsXin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim. 184-190 [doi]
• Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraintLi Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak. 191-196 [doi]
• BIST design optimization for large-scale embedded memory coresTzuo-Fan Chien, Wen-Chi Chao, Chien-Mo Li, Yao-Wen Chang, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng. 197-200 [doi]
• Operating system scheduling for efficient online self-test in robust systemsYanjing Li, Onur Mutlu, Subhasish Mitra. 201-208 [doi]
• Quantifying robustness metrics in parameterized static timing analysisKhaled R. Heloue, Chandramouli V. Kashyap, Farid N. Najm. 209-216 [doi]
• PSTA-based branch and bound approach to the silicon speedpath isolation problemSari Onaissi, Khaled R. Heloue, Farid N. Najm. 217-224 [doi]
• Timing Arc based logic analysis for false noise reductionMurthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler. 225-230 [doi]
• Exact route matching algorithms for analog and mixed signal integrated circuitsMustafa Mustafa Ozdal, Renato Fernandes Hentschke. 231-238 [doi]
• An efficient pre-assignment routing algorithm for flip-chip designsPo-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng. 239-244 [doi]
• Optimal layer assignment for escape routing of busesTan Yan, Hui Kong, Martin D. F. Wong. 245-248 [doi]
• Pad assignment for die-stacking System-in-Package designYu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang. 249-255 [doi]
• Thermal modeling for 3D-ICs with integrated microchannel coolingHitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu. 256-263 [doi]
• Energy reduction for STT-RAM using early write terminationPing Zhou, Bo Zhao, Jun Yang 0002, Youtao Zhang. 264-268 [doi]
• PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAMXiangyu Dong, Norman P. Jouppi, Yuan Xie. 269-275 [doi]
• Introduction to GPU programming for EDAJohn F. Croix, Sunil P. Khatri. 276-280 [doi]
• The epsilon-approximation to discrete VT assignment for leakage power minimizationYujia Feng, Shiyan Hu. 281-287 [doi]
• A rigorous framework for convergent net weighting schemes in timing-driven placementTony F. Chan, Jason Cong, Eric Radke. 288-294 [doi]
• An efficient algorithm for modeling spatially-correlated process variation in statistical full-chip leakage analysisZuochang Ye, Zhiping Yu. 295-301 [doi]
• TAPE: Thermal-aware agent-based power econom multi/many-core architecturesThomas Ebi, Mohammad Abdullah Al Faruque, Jörg Henkel. 302-309 [doi]
• Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency controlVinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha. 310-313 [doi]
• A hybrid local-global approach for multi-core thermal managementRamkumar Jayaseelan, Tulika Mitra. 314-320 [doi]
• A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTAJaeyong Chung, Jacob A. Abraham. 321-327 [doi]
• Binning optimization based on SSTA for transparently-latched circuitsMin Gong, Hai Zhou, Jun Tao, Xuan Zeng. 328-335 [doi]
• Timing model extraction for sequential circuits considering process variationsBing Li, Ning Chen, Ulf Schlichtmann. 333-343 [doi]
• CROP: Fast and effective congestion refinement of placementYanheng Zhang, Chris Chu. 344-350 [doi]
• GRPlacer: Improving routability and wire-length of global routing with circuit replacementKe-Ren Dai, Chien-Hung Lu, Yih-Lang Li. 351-356 [doi]
• CRISP: Congestion reduction by iterated spreading during placementJarrod A. Roy, Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov. 357-362 [doi]
• A study of routability estimation and clustering in placementKalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan. 363-366 [doi]
• The synthesis of combinational logic to generate probabilitiesWeikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja. 367-374 [doi]
• Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuitsSeonggwan Lee, Seungwhun Paik, Youngsoo Shin. 375-380 [doi]
• Synthesizing complementary circuits automaticallyShengYu Shen, Jianmin Zhang, Ying Qin, Sikun Li. 381-388 [doi]
• QLMOR: A new projection-based approach for nonlinear model order reductionChenjie Gu. 389-396 [doi]
• Computing quadratic approximations for the isochrons of oscillators: A general theory and advanced numerical methodsOnder Suvak, Alper Demir. 397-402 [doi]
• Final-value ODEs: Stable numerical integration and its application to parallel circuit analysisWei Dong, Peng Li. 403-409 [doi]
• A parallel preconditioning strategy for efficient transistor-level circuit simulationHeidi Thornquist, Eric R. Keiter, Robert J. Hoekstra, David M. Day, Erik G. Boman. 410-417 [doi]
• Characterizing within-die variation from multiple supply port IDDQ measurementsKanak Agarwal, Dhruva Acharyya, Jim Plusquellic. 418-424 [doi]
• Voltage binning under process variationVladimir Zolotov, Chandu Visweswariah, Jinjun Xiong. 425-432 [doi]
• Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuitsXin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton. 433-440 [doi]
• Post-fabrication measurement-driven oxide breakdown reliability prediction and managementCheng Zhuo, David Blaauw, Dennis Sylvester. 441-448 [doi]
• Minimizing expected energy consumption through optimal integration of DVS and DPMBaoxian Zhao, Hakan Aydin. 449-456 [doi]
• An efficient wakeup scheduling considering resource constraint for sensor-based power gating designsMing-Chao Lee, Yu-Ting Chen, Yo-Tzu Cheng, Shih-Chieh Chang. 457-460 [doi]
• Adaptive power management using reinforcement learningYing Tan, Wei Liu, Qinru Qiu. 461-467 [doi]
• Temporal and spatial idleness exploitation for optimal-grained leakage controlHao Xu, Ranga Vemuri, Wen-Ben Jone. 468-473 [doi]
• A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologiesSubho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay. 474-477 [doi]
• Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakageSoogine Chong, Kerem Akarvardar, Roozbeh Parsa, Jun-Bo Yoon, Roger T. Howe, Subhasish Mitra, H.-S. Philip Wong. 478-484 [doi]
• Nonvolatile memristor memory: Device characteristics and design implicationsYenpo Ho, Garng M. Huang, Peng Li. 485-490 [doi]
• Gene-regulatory memories: Electrical-equivalent modeling, simulation and parameter identificationYong Zhang, Peng Li. 491-496 [doi]
• An elegant hardware-corroborated statistical repair and test methodology for conquering aging effectsRouwaida Kanj, Rajiv V. Joshi, Chad Adams, James Warnock, Sani R. Nassif. 497-504 [doi]
• Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantizationSeid Hadi Rasouli, Kazuhiko Endo, Kaustav Banerjee. 505-512 [doi]
• Modeling of layout-dependent stress effect in CMOS designChi-Chao Wang, Wei Zhao, Frank Liu, Min Chen, Yu Cao. 513-520 [doi]
• Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimizationJiying Xue, Zuochang Ye, Yangdong Deng, Hongrui Wang, Liu Yang, Zhiping Yu. 521-528 [doi]
• Leveraging efficient parallel pattern search for clock mesh optimizationXiaoji Ye, Srinath Narasimhan, Peng Li. 529-534 [doi]
• Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designsYu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang. 535-538 [doi]
• Taming irregular EDA applications on GPUsYangdong Deng, Bo D. Wang, Shuai Mu. 539-546 [doi]
• Multi-level clustering for clock skew optimizationJonas Casanova, Jordi Cortadella. 547-554 [doi]
• From 2D to 3D NoCs: A case study on worst-case communication performanceYue Qian, Zhonghai Lu, Wenhua Dou. 555-562 [doi]
• An accurate and efficient performance analysis approach based on queuing model for network on chipMing-che Lai, Lei Gao, Nong Xiao, Zhiying Wang. 563-570 [doi]
• A performance analytical model for Network-on-Chip with constant service time routersNikita Nikitin, Jordi Cortadella. 571-578 [doi]
• A method for calculating hard QoS guarantees for Networks-on-ChipDara Rahmati, Srinivasan Murali, Luca Benini, Federico Angiolini, Giovanni De Micheli, Hamid Sarbazi-Azad. 579-586 [doi]
• Task management in MPSoCs: An ASIP approachJerónimo Castrillón, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid. 587-594 [doi]
• Simultaneous layout migration and decomposition for double patterning technologyChin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif. 595-600 [doi]
• GREMA: Graph reduction based efficient mask assignment for double patterning technologyYue Xu, Chris Chu. 601-606 [doi]
• Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithographyMohit Gupta, Kwangok Jeong, Andrew B. Kahng. 607-614 [doi]
• A framework for early and systematic evaluation of design rulesRani S. Ghaida, Puneet Gupta. 615-622 [doi]
• Adaptive sampling for efficient failure probability analysis of SRAM cellsJavid Jaffari, Mohab Anis. 623-630 [doi]
• Yield estimation of SRAM circuits using Virtual SRAM Fab Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das. 631-636 [doi]
• Mitigation of intra-array SRAM variability using adaptive voltage architectureAshish Kumar Singh, Ku He, Constantine Caramanis, Michael Orshansky. 637-644 [doi]
• Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICsYoung-Joon Lee, Rohan Goel, Sung Kyu Lim. 645-651 [doi]
• Energy-optimal dynamic thermal management for green computingDonghwa Shin, Jihun Kim, Naehyuck Chang, Jinhang Choi, Sung Woo Chung, Eui-Young Chung. 652-657 [doi]
• Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologiesChuan Xu, Lijun Jiang, Seshadri K. Kolluri, Barry J. Rubin, Alina Deutsch, Howard Smith, Kaustav Banerjee. 658-665 [doi]
• Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designsYi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang. 666-673 [doi]
• A study of Through-Silicon-Via impact on the 3D stacked IC layoutDae-Hyun Kim, Krit Athikulwongse, Sung Kyu Lim. 674-680 [doi]
• Parallel multi-level analytical global placement on graphics processing unitsJason Cong, Yi Zou. 681-688 [doi]
• Memory organization and data layout for instruction set extensions with architecturally visible storagePanagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne. 689-696 [doi]
• Automatic memory partitioning and scheduling for throughput and power optimizationJason Cong, Wei Jiang, Bin Liu, Yi Zou. 697-704 [doi]
• Battery allocation for wireless sensor network lifetime maximization under cost constraintsHengyu Long, Yongpan Liu, Yiqun Wang, Robert P. Dick, Huazhong Yang. 705-712 [doi]
• Genetic design automationChris J. Myers, Nathan A. Barker, Hiroyuki Kuwahara, Kevin Jones, Curtis Madsen, Nam-Phuong D. Nguyen. 713-716 [doi]
• An electrical-level superposed-edge approach to statistical serial link simulationMichael J. Tsuk, Daniel Dvorscak, Chin Siong Ong, Jacob White. 717-724 [doi]
• Joint design-time and post-silicon optimization for digitally tuned analog circuitsWei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti. 725-730 [doi]
• Fast trade-off evaluation for digital signal processing systems during wordlength optimizationLinsheng Zhang, Yan Zhang, Wenbiao Zhou. 731-738 [doi]
• Improved heuristics for finite word-length polynomial datapath optimizationBijan Alizadeh, Masahiro Fujita. 739-744 [doi]
• Decoupling capacitance efficient placement for reducing transient power supply noiseXiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. Tan, Thom Jefferson A. Eguia. 745-751 [doi]
• A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extractionTarek A. El-Moselhy, Ibrahim M. Elfadel, Luca Daniel. 752-758 [doi]
• Active-passive co-synthesis of multi-GigaHertz radio frequency circuits with broadband parametric macromodels of on-chip passivesRitochit Chakraborty, Arun V. Sathanur, Vikram Jandhyala. 759-766 [doi]
• GHM: A generalized Hamiltonian method for passivity test of impedance/admittance descriptor systemsZheng Zhang, Chi-Un Lei, Ngai Wong. 767-773 [doi]
• Fast and reliable passivity assessment and enforcement with extended Hamiltonian pencilZuochang Ye, Luis Miguel Silveira, Joel R. Phillips. 774-778 [doi]
• Interpolating functions from large Boolean relationsJie-Hong Roland Jiang, Hsuan-Po Lin, Wei-Lun Hung. 779-784 [doi]
• Fast detection of node mergers using logic implicationsYung-Chih Chen, Chun-Yao Wang. 785-788 [doi]
• DeltaSyn: An efficient logic difference optimizer for ECO synthesisSmita Krishnaswamy, Haoxing Ren, Nilesh Modi, Ruchir Puri. 789-796 [doi]
• Iterative layering: Optimizing arithmetic circuits by structuring the information flowAjay K. Verma, Philip Brisk, Paolo Ienne. 797-804 [doi]
• Global routing revisitedMichael D. Moffitt. 805-808 [doi]
• POWER7 - Verification challenge of a multi-core processorKlaus-Dieter Schubert. 809-812 [doi]