Ming-che Lai - researchr alias

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Viewing Publication 1 - 29 from 29

2022

SpacKV: A Pmem-Aware Key-Value Separation Store Based on LSM-TreeXuran Ge, Ming-che Lai, Yang Liu, Lizhou Wu, Zhutao Zhuang, Yang Ou, Zhiguang Chen, Nong Xiao. npc 2022: 327-339 [doi]

2018

Moving from exascale to zettascale computing: challenges and techniquesXiangke Liao, Kai Lu, Canqun Yang, Jin-wen Li, Yuan Yuan, Ming-che Lai, Li-Bo Huang, Ping-jing Lu, Jian-bin Fang, Jing Ren, Jie Shen 0003. jzusc, 19(10):1236-1244, 2018. [doi]

2014

Holistic Routing Algorithm Design to Support Workload Consolidation in NoCsSheng Ma, Natalie D. Enright Jerger, Zhiying Wang, Ming-che Lai, Libo Huang. TC, 63(3):529-542, 2014. [doi]

2013

2011

2010

A hybrid algorithm for capacitated plant location problemMing-che Lai, Hansuk Sohn, Tzu-Liang (Bill) Tseng, Chunkuan Chiang. eswa, 37(12):8599-8605, 2010. [doi]

Exploration and implementation of a highly efficient processor element for multimedia and signal processing domainsMing-che Lai, Lei Gao, Zhiying Wang. iet-cdt, 4(5):374-387, 2010. [doi]

2009

A Practical Non-blocking Route Propagation Technology for Threaded BGPLai Gao, Ming-che Lai, Zhenghu Gong. scalcom 2009: 206-211 [doi]

An Improved Parallel Access Technology on Routing Table for Threaded BGPLei Gao, Ming-che Lai, Zhenghu Gong. icpads 2009: 198-204 [doi]

An accurate and efficient performance analysis approach based on queuing model for network on chipMing-che Lai, Lei Gao, Nong Xiao, Zhiying Wang. iccad 2009: 563-570 [doi]

2008

A TLP approach for BGP based on local speculationLei Gao, Zhenghu Gong, Yaping Liu, Ming-che Lai, Wei Peng. chinaf, 51(11):1772-1784, 2008. [doi]

The P2P Communication Model for a Local Memory based Multi-core ProcessorJianjun Guo, Kui Dai, Ming-che Lai, Zhiying Wang. icycs 2008: 1354-1359 [doi]

Hierarchical memory system design for a heterogeneous multi-core processorJianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang. SAC 2008: 1504-1508 [doi]

Memory System Design for a Multi-core ProcessorJianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang. cisis 2008: 601-606 [doi]

Using an Automated Approach to Explore and Design a High-Efficiency Processor Element for the Multimedia DomainMing-che Lai, Jianjun Guo, Zhuxi Zhang, Zhiying Wang. cisis 2008: 613-618 [doi]

A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routersMing-che Lai, Zhiying Wang, Lei Gao, Hongyi Lu, Kui Dai. dac 2008: 630-633 [doi]

Escaping from Blocking: A Dynamic Virtual Channel for Pipelined RoutersMing-che Lai, Lei Gao, Wei Shi, Zhiying Wang. cisis 2008: 795-800 [doi]

Exploiting the Thread-Level Parallelism for BGP on Multi-coreGao Lei, Ming-che Lai, Zhenghu Gong. cnsr 2008: 510-516 [doi]

2007

2006

A Novel Data-Parallel Coprocessor for Multimedia Signal ProcessingMing-che Lai, Kui Dai, Lu Hong-yi, Zhiying Wang. icmcs 2006: 369-372 [doi]

2005

Design of a Configurable Embedded Processor Architecture for DSP FunctionsHong Yue, Ming-che Lai, Kui Dai, Zhiying Wang. icpads 2005: 27-31 [doi]

2004

A New Technique for Program Code Compression in Embedded MicroprocessorMing-che Lai, Kui Dai, Li Shen, Zhiying Wang. icess 2005: 158-164 [doi]

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