Table of Contents

• A compositional modelling framework for exploring MPSoC systemsAnders Sejer Tranberg-Hansen, Jan Madsen. 1-10 [doi]
• A high-level virtual platform for early MPSoC software developmentJianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 11-20 [doi]
• Portable SystemC-on-a-chipScott Sirowy, Bailey Miller, Frank Vahid. 21-30 [doi]
• On compile-time evaluation of process partitioning transformations for Kahn process networksSjoerd Meijer, Hristo Nikolov, Todor Stefanov. 31-40 [doi]
• SARA: StreAm register allocationPraveen Raghavan, Francky Catthoor. 41-50 [doi]
• Dynamically utilizing computation accelerators for extensible processors in a software approachYa-shuai Lü, Li Shen, Zhiying Wang, Nong Xiao. 51-60 [doi]
• An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checkingWeichen Liu, Zonghua Gu, Jiang Xu, Yu Wang 0002, Mingxuan Yuan. 61-70 [doi]
• Using binary translation in event driven simulation for fast and flexible MPSoC simulationMarius Gligor, Nicolas Fournel, Frédéric Pétrot. 71-80 [doi]
• Configuration and control of SystemC models using TLM middlewareChristian Schröder, Wolfgang Klingauf, Robert Günzel, Mark Burton, Eric Roesler. 81-88 [doi]
• Scalable and retargetable simulation techniquesfor multiprocessor systemsHeekyung Kim, Dukyoung Yun, Soonhoi Ha. 89-98 [doi]
• An on-chip interconnect and protocol stack for multiple communication paradigms and programming modelsAndreas Hansson, Kees Goossens. 99-108 [doi]
• A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architecturesLeonel Tedesco, Fabien Clermidy, Fernando Moraes. 109-118 [doi]
• A DP-network for optimal dynamic routing in network-on-chipTerrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam. 119-128 [doi]
• Exploring hybrid photonic networks-on-chip foremerging chip multiprocessorsShirish Bahirat, Sudeep Pasricha. 129-136 [doi]
• LOP: a novel SRAM-based architecture for low power and high throughput packet classificationXin He, Jorgen Peddersen, Sri Parameswaran. 137-146 [doi]
• Memory-efficient distribution of regular expressions for fast deep packet inspectionJonathan Rohrer, Kubilay Atasu, Jan van Lunteren, Christoph Hagleitner. 147-154 [doi]
• On-the-fly hardware acceleration for protocol stack processing in next generation mobile devicesDavid Szczesny, Sebastian Hessel, Felix Bruns, Attila Bilgic. 155-162 [doi]
• FRA: a flash-aware redundancy array of flash storage devicesYangsup Lee, Sanghyuk Jung, Yong Ho Song. 163-172 [doi]
• Automatic customization of device drivers for IP-cores used with assorted CPU organizationsAndrea Acquaviva, Nicola Bombieri, Franco Fummi, Sara Vinco. 173-182 [doi]
• An MDP-based application oriented optimal policy for wireless sensor networksArslan Munir, Ann Gordon-Ross. 183-192 [doi]
• A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systemsAlireza Ejlali, Bashir M. Al-Hashimi, Petru Eles. 193-202 [doi]
• Efficient dynamic voltage/frequency scaling through algorithmic loop transformationMohammad Ali Ghodrat, Tony Givargis. 203-210 [doi]
• Energy-efficiency for multiframe real-time tasks on a dynamic voltage scaling processorChuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo. 211-220 [doi]
• A variation-tolerant scheduler for better than worst-case behavioral synthesisJason Cong, Albert Liu, Bin Liu. 221-228 [doi]
• Exploiting data-redundancy in reliability-aware networked embedded system designMartin Lukasiewycz, Michael Glaß, Jürgen Teich. 229-238 [doi]
• ESL power analysis of embedded processors for temperature and reliability estimationsBjörn Sander, Jürgen Schnerr, Oliver Bringmann. 239-248 [doi]
• Squashing microcode stores to size in embedded systems while delivering rapid microcode accessesChengmo Yang, Mingjing Chen, Alex Orailoglu. 249-256 [doi]
• Stack oriented data cache filteringRodrigo González-Alberquilla, Fernando Castro, Luis Piñuel, Francisco Tirado. 257-266 [doi]
• ILP optimal scheduling for multi-module memoryMeikang Qiu, Lei Zhang, Edwin Hsing-Mean Sha. 277-286 [doi]
• Cycle count accurate memory modeling in system level designYi-Len Lo, Mao Lin Li, Ren-Song Tsay. 287-294 [doi]
• SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systemsMohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran. 295-304 [doi]
• TotalProf: a fast and accurate retargetable source code profilerLei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 305-314 [doi]
• Using continuous statistical machine learning to enable high-speed performance prediction in hybrid instruction-/cycle-accurate instruction set simulatorsDaniel Christopher Powell, Björn Franke. 315-324 [doi]
• Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systemsVincenzo Rana, Srinivasan Murali, David Atienza, Marco D. Santambrogio, Luca Benini, Donatella Sciuto. 325-334 [doi]
• MinDeg: a performance-guided replacement policy for run-time reconfigurable acceleratorsLars Bauer, Muhammad Shafique, Jörg Henkel. 335-342 [doi]
• Supporting RTL flow compatibility in a microarchitecture-level design frameworkDaniel Schwartz-Narbonne, Carven Chan, Yogesh S. Mahajan, Sharad Malik. 343-352 [doi]
• A scalable parallel H.264 decoder on the cell broadband engine architectureMichael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula. 353-362 [doi]
• FlexRay schedule optimization of the static segmentMartin Lukasiewycz, Michael Glaß, Jürgen Teich, Paul Milbredt. 363-372 [doi]
• Improving application launch times with hybrid disksYongsoo Joo, Youngjin Cho, Kyungsoo Lee, Naehyuck Chang. 373-382 [doi]
• A tuneable software cache coherence protocol for heterogeneous MPSoCsFrank E. B. Ophelders, Marco Bekooij, Henk Corporaal. 383-392 [doi]
• Building heterogeneous reconfigurable systems with a hardware microkernelJason Agron, David L. Andrews. 393-402 [doi]
• Native MPSoC co-simulation environment for software performance estimationPatrice Gerin, Mian Muhammad Hamayun, Frédéric Pétrot. 403-412 [doi]
• Fast model-based test case classification for performance analysis of multimedia MPSoC platformsDeepak Gangadharan, Samarjit Chakraborty, Roger Zimmermann. 413-422 [doi]
• Bottom-up performance analysis considering time slice based software scheduling at system levelAlexander Viehl, Michael Pressler, Oliver Bringmann. 423-432 [doi]
• A recursive approach to end-to-end path latency computation in heterogeneous multiprocessor systemsSimon Schliecker, Rolf Ernst. 433-442 [doi]
• Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approachAntonino Tumeo, Marco Branca, Lorenzo Camerini, Christian Pilato, Pier Luca Lanzi, Fabrizio Ferrandi, Donatella Sciuto. 443-452 [doi]
• Applying network calculus for performance analysis of self-similar traffic in on-chip networksYue Qian, Zhonghai Lu, Wenhua Dou. 453-460 [doi]
• Statistical physics approaches for network-on-chip traffic characterizationPaul Bogdan, Radu Marculescu. 461-470 [doi]
• Automated technique for design of NoC with minimal communication latencyGlenn Leary, Karam S. Chatha. 471-480 [doi]
• Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chipMatthias Bo Stuart, Mikkel Bystrup Stensgaard, Jens Sparsø. 481-490 [doi]