Table of Contents

• Application and realization of gateways between conventional automotive and IP/ethernet-based networksHelge Zinner, Josef Nöbauer, Thomas Gallner, Jochen Seitz, Thomas Waas. 1-6 [doi]
• Challenges in a future IP/ethernet-based in-car network for real-time applicationsHyung Taek Lim, Lars Völker, Daniel Herrscher. 7-12 [doi]
• Rigorous model-based design & verification flow for in-vehicle softwareS. Ramesh, Ambar A. Gadkari. 13-16 [doi]
• MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systemsZhiwei Qin, Yi Wang 0003, Duo Liu, Zili Shao, Yong Guan. 17-22 [doi]
• Plugging versus logging: a new approach to write buffer management for solid-state disksLi-Pin Chang, You-Chiuan Su. 23-28 [doi]
• A version-based strategy for reliability enhancement of flash file systemsPei-Han Hsu, Yuan-Hao Chang, Po-Chun Huang, Tei-Wei Kuo, David Hung-Chang Du. 29-34 [doi]
• Understanding the impact of power loss on flash memoryHung-Wei Tseng, Laura M. Grupp, Steven Swanson. 35-40 [doi]
• Deriving a near-optimal power management policy using model-free reinforcement learning and Bayesian classificationYanzhi Wang, Qing Xie, Ahmed C. Ammari, Massoud Pedram. 41-46 [doi]
• PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designsChen-Wei Hsu, Jia-Lu Liao, Shan Chien Fang, Chia-Chien Weng, Shi-Yu Huang, Wen-Tsan Hsieh, Jen-Chieh Yeh. 47-52 [doi]
• Dynamic voltage scaling of OLED displaysDonghwa Shin, Younghyun Kim, Naehyuck Chang, Massoud Pedram. 53-58 [doi]
• Power management of hybrid DRAM/PRAM-based main memoryHyunsun Park, Sungjoo Yoo, Sunggu Lee. 59-64 [doi]
• To DFM or not to DFM?Wing Chiu Tam, R. D. (Shawn) Blanton. 65-70 [doi]
• Self-aligned double patterning decomposition for overlay minimization and hot spot detectionHongbo Zhang, Yuelin Du, Martin D. F. Wong, Rasit Onur Topaloglu. 71-76 [doi]
• Statistical characterization of standard cells using design of experiments with response surface modelingMiguel Miranda, Philippe Roussel, Lucas Brusamarello, Gilson I. Wirth. 77-82 [doi]
• Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometriesNikolai Ryzhenko, Steven Burns. 83-88 [doi]
• Dimetrodon: processor-level preventive thermal management via idle cycle injectionPeter Bailis, Vijay Janapa Reddi, Sanjay Gandhi, David Brooks, Margo I. Seltzer. 89-94 [doi]
• Dynamic thermal management for multimedia applications using machine learningYang Ge, Qinru Qiu. 95-100 [doi]
• Improved post-silicon power modeling using AC lock-in techniquesAbdullah Nazma Nowroz, Gary Woods, Sherief Reda. 101-106 [doi]
• Thermal signature: a simple yet accurate thermal index for floorplan optimizationJaeha Kung, Inhak Han, Sachin S. Sapatnekar, Youngsoo Shin. 108-113 [doi]
• Joint DAC/IWBDA special session design and synthesis of biological circuitsDouglas Densmore, Mark Horowitz, Smita Krishnaswamy, Xiling Shen, Adam Arkin, Erik Winfree, Chris Voigt. 114-115 [doi]
• Modeling adaptive streaming applications with parameterized polyhedral process networksJiali Teddy Zhai, Hristo Nikolov, Todor Stefanov. 116-121 [doi]
• Compilation of stream programs onto scratchpad memory based embedded multicore processors through retimingWeijia Che, Karam S. Chatha. 122-127 [doi]
• CuMAPz: a tool to analyze memory access patterns in CUDAYooseong Kim, Aviral Shrivastava. 128-133 [doi]
• SEAL: soft error aware low power scheduling by Monte Carlo state space under the influence of stochastic spatial and temporal dependenciesNabeel Iqbal, Muhammad Adnan Siddique, Jörg Henkel. 134-139 [doi]
• Simultaneous functional and timing ECOHua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang. 140-145 [doi]
• Interpolation-based incremental ECO synthesis for multi-error logic rectificationKai-Fu Tang, Chi-An Wu, Po-Kai Huang, Chung-Yang (Ric) Huang. 146-151 [doi]
• Optimal multi-domain clock skew schedulingLi Li 0021, Yinghai Lu, Hai Zhou. 152-157 [doi]
• Re-synthesis for cost-efficient circuit-level timing speculationYuxi Liu, Feng Yuan, Qiang Xu. 158-163 [doi]
• An exact algorithm for the construction of rectilinear Steiner minimum trees among complex obstaclesTao Huang, Evangeline F. Y. Young. 164-169 [doi]
• Gridless pin access in detailed routingTim Nieberg. 170-175 [doi]
• An optimal algorithm for layer assignment of bus escape routing on PCBsQiang Ma 0002, Evangeline F. Y. Young, Martin D. F. Wong. 176-181 [doi]
• A distributed algorithm for layout geometry operationsKai-Ti Hsu, Subarna Sinha, Yu-Chuan Pi, Charles Chiang, Tsung-Yi Ho. 182-187 [doi]
• TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D ICMoongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim. 188-193 [doi]
• Hybrid modeling of non-stationary process variationsEva L. Dyer, Mehrdad Majzoobi, Farinaz Koushanfar. 194-199 [doi]
• Efficient SRAM failure rate prediction via Gibbs samplingChangdao Dong, Xin Li. 200-205 [doi]
• Direct matrix solution of linear complexity for surface integral-equation based impedance extraction of high bandwidth interconnectsWenwen Chai, Dan Jiao. 206-211 [doi]
• Design, CAD and technology challenges for future processors: 3D perspectivesJeff Burns, Gary Carpenter, Eren Kursun, Ruchir Puri, James D. Warnock, Michael Scheuermann. 212 [doi]
• 3D heterogeneous system integration: application driver for 3D technology developmentEric Beyne, Pol Marchal, Geert Van der Plas. 213 [doi]
• 3D integration for energy efficient system designShekhar Borkar. 214-219 [doi]
• Applications driving 3D integration and corresponding manufacturing challengesRasit Onur Topaloglu. 220-223 [doi]
• Test-case generation for embedded simulink via formal concept analysisNannan He, Philipp Rümmer, Daniel Kroening. 224-229 [doi]
• A first step towards automatic application of power analysis countermeasuresAli Galip Bayrak, Francesco Regazzoni, Philip Brisk, François-Xavier Standaert, Paolo Ienne. 230-235 [doi]
• TPM-SIM: a framework for performance evaluation of trusted platform modulesJared Schmitz, Jason Loew, Jesse Elwell, Dmitry Ponomarev, Nael B. Abu-Ghazaleh. 236-241 [doi]
• Differential public physically unclonable functions: architecture and applicationsMiodrag Potkonjak, Saro Meguerdichian, Ani Nahapetian, Sheng Wei. 242-247 [doi]
• Integrated circuit security techniques using variable supply voltageSheng Wei, Miodrag Potkonjak. 248-253 [doi]
• Information flow isolation in I2C and USBJason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Ryan Kastner. 254-259 [doi]
• CIRUS: a scalable modular architecture for reusable driversBratin Saha. 260-261 [doi]
• Programming challenges & solutions for multi-processor SoCs: an industrial perspectivePierre G. Paulin. 262-267 [doi]
• Thermal-aware system analysis and software synthesis for embedded multi-processorsLothar Thiele, Lars Schor, Hoeseok Yang, Iuliana Bacivarov. 268-273 [doi]
• Temporal isolation on multiprocessing architecturesDai N. Bui, Edward A. Lee, Isaac Liu, Hiren D. Patel, Jan Reineke. 274-279 [doi]
• Physics-based field-theoretic design automation tools for social networks and web searchVikram Jandhyala. 280-281 [doi]
• Can we go towards true 3-D architectures?Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Paul-Henry Morel, Jean-Philippe Noël, Fabien Clermidy, Ian O'Connor. 282-283 [doi]
• Orchestrated multi-level information flow analysis to understand SoCsGörschwin Fey. 284-285 [doi]
• Dynamic binary translation to a reconfigurable target for on-the-fly accelerationPhillip Kinsman, Nicola Nicolici. 286-287 [doi]
• Device aging-based physically unclonable functionsSaro Meguerdichian, Miodrag Potkonjak. 288-289 [doi]
• Significance driven computation on next-generation unreliable platformsGeorgios Karakonstantis, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Tziantzioulis, Vaibhav Gupta, Kaushik Roy. 290-291 [doi]
• MUSTARD: a coupled, stochastic/deterministic, discrete/continuous technique for predicting the impact of random telegraph noise on SRAMs and DRAMsKarthik V. Aadithya, Sriramkumar Venugopalan, Alper Demir, Jaijeet S. Roychowdhury. 292-297 [doi]
• Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomialsFang Gong, Hao Yu, Lei He. 298-303 [doi]
• Automatic stability checking for large linear analog integrated circuitsParijat Mukherjee, G. Peter Fang, Rod Burt, Peng Li. 304-309 [doi]
• Performance bound analysis of analog circuits considering process variationsZhigang Hao, Sheldon X.-D. Tan, Ruijing Shen, Guoyong Shi. 310-315 [doi]
• Rethinking memory redundancy: optimal bit cell repair for maximum-information storageXin Li. 316-321 [doi]
• Programmable analog device array (PANDA): a platform for transistor-level analog reconfigurabilityRui Zheng, Jounghyuk Suh, Cheng Xu, Nagib Hakim, Bertan Bakkaloglu, Yu Cao. 322-327 [doi]
• Complexity and the challenges of securing SoCsPaul Kocher. 328-331 [doi]
• High-performance energy-efficient encryption in the sub-45nm CMOS EraRam Krishnamurthy, Sanu Mathew, Farhana Sheikh. 332 [doi]
• The state-of-the-art in semiconductor reverse engineeringRandy Torrance, Dick James. 333-338 [doi]
• A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulationMeng-Huan Wu, Peng-Chih Wang, Cheng-Yang Fu, Ren-Song Tsay. 339-344 [doi]
• Simulation environment configuration for parallel simulation of multicore embedded systemsDukyoung Yun, Jinwoo Kim, Sungchan Kim, Soonhoi Ha. 345-350 [doi]
• Transaction level statistical analysis for efficient micro-architectural power and performance studiesEman Copty, Gila Kamhi, Sasha Novakovsky. 351-356 [doi]
• Extracting behavior and dynamically generated hierarchy from SystemC modelsHarry Broeders, René van Leuken. 357-362 [doi]
• Throughput maximization for periodic real-time systems under the maximal temperature constraintHuang Huang, Gang Quan, Jeffrey Fan, Meikang Qiu. 363-368 [doi]
• Performance optimization of error detection based on speculative reconfigurationAdrian Alin Lifa, Petru Eles, Zebo Peng. 369-374 [doi]
• On the quantification of sustainability and extensibility of FlexRay schedulesReinhard Schneider 0001, Dip Goswami, Samarjit Chakraborty, Unmesh D. Bordoloi, Petru Eles, Zebo Peng. 375-380 [doi]
• Generalized reliability-oriented energy management for real-time embedded applicationsBaoxian Zhao, Hakan Aydin, Dakai Zhu. 381-386 [doi]
• Customer-aware task allocation and scheduling for multi-mode MPSoCsLin Huang, Rong Ye, Qiang Xu. 387-392 [doi]
• Symbolic system synthesis in the presence of stringent real-time constraintsFelix Reimann, Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich. 393-398 [doi]
• Supervised design space exploration by compositional approximation of Pareto setsHung-Yi Liu, Ilias Diakonikolas, Michele Petracca, Luca P. Carloni. 399-404 [doi]
• Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memoryTiantian Liu, Yingchao Zhao, Chun Jason Xue, Minming Li. 405-410 [doi]
• TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overheadFlavio M. de Paula, Amir Nahir, Ziv Nevo, Avigail Orni, Alan J. Hu. 411-416 [doi]
• Testability driven statistical path selectionJaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham. 417-422 [doi]
• Diagnosing scan clock delay faults through statistical timing pruningMingjing Chen, Alex Orailoglu. 423-428 [doi]
• Diagnosis of transition fault clustersIrith Pomeranz. 429-434 [doi]
• Leakage-aware redundancy for reliable sub-threshold memoriesSeokjoong Kim, Matthew R. Guthaus. 435-440 [doi]
• A 40 nm inverse-narrow-width-effect-aware sub-threshold standard cell libraryJun Zhou, Senthil Jayapal, Ben Busze, Li Huang, Jan Stuyt. 441-446 [doi]
• Layout aware line-edge roughness modeling and poly optimization for leakage minimizationYongchan Ban, Jae-Seok Yang. 447-452 [doi]
• Post sign-off leakage power optimizationHamed Abrishami, Jinan Lou, Jeff Qin, Juergen Froessl, Massoud Pedram. 453-458 [doi]
• Lithography at 14nm and beyond: choices and challengesVivek Singh. 459 [doi]
• New sub-20nm transistors: why and howChenming Hu. 460-463 [doi]
• Circuit design challenges at the 14nm technology nodeJames D. Warnock. 464-467 [doi]
• Cool shapers: shaping real-time tasks for improved thermal guaranteesPratyush Kumar, Lothar Thiele. 468-473 [doi]
• ChronOS Linux: a best-effort real-time multiprocessor Linux kernelMatthew Dellinger, Piyush Garyali, Binoy Ravindran. 474-479 [doi]
• Efficient WCRT analysis of synchronous programs using reachabilityMatthew Kuo, Roopak Sinha, Partha S. Roop. 480-485 [doi]
• Fast and accurate source-level simulation of software timing considering complex code optimizationsStefan Stattelmann, Oliver Bringmann, Wolfgang Rosenstiel. 486-491 [doi]
• Abstraction-based performance verification of NoCsDaniel E. Holcomb, Bryan A. Brady, Sanjit A. Seshia. 492-497 [doi]
• Global convergence analysis of mixed-signal systemsSangho Youn, Jaeha Kim, Mark Horowitz. 498-503 [doi]
• Litmus tests for comparing memory consistency models: how long do they need to be?Sela Mador-Haim, Rajeev Alur, Milo M. K. Martin. 504-509 [doi]
• Formal hardware/software co-verification by interval property checking with abstractionMinh D. Nguyen, Markus Wedler, Dominik Stoffel, Wolfgang Kunz. 510-515 [doi]
• Distributed Resonant clOCK grid Synthesis (ROCKS)Xuchu Hu, Matthew R. Guthaus. 516-521 [doi]
• WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizingDeokjin Joo, Taewhan Kim. 522-527 [doi]
• Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuitsCheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang. 528-533 [doi]
• Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effectJim Aarestad, Charles Lamech, Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal. 534-539 [doi]
• A stabilized discrete empirical interpolation method for model reduction of electrical, thermal, and microelectromechanical systemsAmit Hochman, Bradley N. Bond, Jacob K. White. 540-545 [doi]
• A novel framework for passive macro-modelingZuochang Ye, Yang Li, Mingzhi Gao, Zhiping Yu. 546-551 [doi]
• A highly scalable parallel boundary element method for capacitance extractionYu-Chung Hsiao, Luca Daniel. 552-557 [doi]
• Fast multipole method on GPU: tackling 3-D capacitance extraction on massively parallel SIMD platformsXueqian Zhao, Zhuo Feng. 558-563 [doi]
• Transaction based pre-to-post silicon validationEli Singerman, Yael Abarbanel, Sean Baartmans. 564-568 [doi]
• Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processorAllon Adir, Amir Nahir, Gil Shurek, Avi Ziv, Charles Meissner, John Schumann. 569-574 [doi]
• A method to leverage pre-silicon collateral and analysis for post-silicon testing and validationGary Miller, Bandana Bhattarai, Yu-Chin Hsu, Jay Dutt, Xi Chen, George Bakewell. 575-578 [doi]
• Energy-efficient MIMO detection using unequal error protection for embedded joint decoding systemYoon Seok Yang, Pankaj Bhagawat, Gwan Choi. 579-584 [doi]
• An algorithm-architecture co-design framework for gridding reconstruction using FPGAsSrinidhi Kestur, Kevin M. Irick, Sungho Park, Ahmed Al-Maashri, Vijaykrishnan Narayanan, Chaitali Chakrabarti. 585-590 [doi]
• A low-energy computation platform for data-driven biomedical monitoring algorithmsMohammed Shoaib, Niraj K. Jha, Naveen Verma. 591-596 [doi]
• Accuracy of ethernet AVB time synchronization under varying temperature conditions for automotive networksAndreas Kern, Helge Zinner, Thilo Streichert, Josef Nöbauer, Jürgen Teich. 597-602 [doi]
• Dynamic effort scaling: managing the quality-efficiency tradeoffVinay K. Chippa, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar. 603-608 [doi]
• Emulation based high-accuracy throughput estimation for high-speed connectivities: case study of USB2.0Byungchul Hong, Chulho Shin, Daehyup Ko. 609-614 [doi]
• Implicit permutation enumeration networks and binary decision diagrams reorderingStergios Stergiou. 615-620 [doi]
• Using SAT-based Craig interpolation to enlarge clock gating functionsTing-Hao Lin, Chung-Yang (Ric) Huang. 621-626 [doi]
• Power reduction via separate synthesis and physical librariesMohammad Rahman, Ryan Afonso, Hiran Tennakoon, Carl Sechen. 627-632 [doi]
• Are logic synthesis tools robust?Alberto Puggelli, Tobias Welp, Andreas Kuehlmann, Alberto L. Sangiovanni-Vincentelli. 633-638 [doi]
• Layout effects in fine grain 3D integrated regular microprocessor blocksVivek S. Nandakumar, Malgorzata Marek-Sadowska. 639-644 [doi]
• Fault-tolerant 3D clock networkChiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang. 645-651 [doi]
• An integrated algorithm for 3D-IC TSV assignmentXiaodong Liu, Yifan Zhang, Gary K. Yeap, Xuan Zeng. 652-657 [doi]
• Non-uniform micro-channel design for stacked 3D-ICsBing Shi, Ankur Srivastava, Peng Wang. 658-663 [doi]
• TSV-aware analytical placement for 3D IC designsMeng-Kai Hsu, Yao-Wen Chang, Valeriy Balabanov. 664-669 [doi]
• Thermal-aware cell and through-silicon-via co-placement for 3D ICsJason Cong, Guojie Luo, Yiyu Shi. 670-675 [doi]
• Efficient incremental analysis of on-chip power grid via sparse approximationPei Sun, Xin Li, Ming Yuan Ting. 676-681 [doi]
• Power grid verification using node and branch dominanceNahi H. Abdul Ghani, Farid N. Najm. 682-687 [doi]
• Power grid correction using sensitivity analysis under an RC modelPamela Al Haddad, Farid N. Najm. 688-693 [doi]
• Design sensitivity of single event transients in scaled logic circuitsJyothi Velamala, Robert LiVolsi, Myra Torres, Yu Cao. 694-699 [doi]
• Designing ad-hoc scrubbing sequences to improve memory reliability against soft errorsPedro Reviriego, Juan Antonio Maestro, Sanghyeon Baeg. 700-705 [doi]
• In-field aging measurement and calibration for power-performance optimizationShuo Wang, Mohammad Tehranipoor, LeRoy Winemberg. 706-711 [doi]
• Single-molecule electronic detection using nanoscale field-effect devicesSebastian Sorgenfrei, Kenneth L. Shepard. 712-717 [doi]
• CMOS compatible nanowires for biosensingEric Stern, David A. Routenberg, Aleksandar Vacic, Nitin K. Rajan, Jason M. Criscione, Jason Park, Tarek M. Fahmy, Mark Reed. 718-722 [doi]
• Heterogeneous integration of carbon nanotubes and graphene microassemblies for environmental and breath sensingSameer Sonkusale, Mehmet R. Dokmeci. 723-728 [doi]
• An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS coresVinay Saripalli, Asit K. Mishra, Suman Datta, Vijaykrishnan Narayanan. 729-734 [doi]
• Device modeling and system simulation of nanophotonic on-chip networks for reliability, power and performanceZheng Li, Moustafa Mohamed, Xi Chen, Alan Rolf Mickelson, Li Shang. 735-740 [doi]
• Progressive network-flow based power-aware broadcast addressing for pin-constrained digital microfluidic biochipsTsung-Wei Huang, Hong-Yan Su, Tsung-Yi Ho. 741-746 [doi]
• Design of robust metabolic pathwaysRenato Umeton, Giovanni Stracquadanio, Anilkumar Sorathiya, Pietro Liò, Alessio Papini, Giuseppe Nicosia. 747-752 [doi]
• Reliability analysis and improvement for multi-level non-volatile memories with soft informationShih-Liang Chen, Bo-Ru Ke, Jian-Nan Chen, Chih-Tsun Huang. 753-758 [doi]
• Image quality aware metrics for performance specification of ADC array in 3D CMOS imagersHsiu-Ming Chang, Kwang-Ting (Tim) Cheng. 759-764 [doi]
• High effective-resolution built-in jitter characterization with quantization noise shapingLeyi Yin, Yongtae Kim, Peng Li. 765-770 [doi]
• A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testingChin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang. 771-776 [doi]
• A fast approach for static timing analysis covering all PVT cornersSari Onaissi, Feroze Taraporevala, Jinfeng Liu, Farid N. Najm. 777-782 [doi]
• Full-chip TSV-to-TSV coupling analysis and optimization in 3D ICChang Liu, Taigon Song, Jonghyun Cho, Joohee Kim, Joungho Kim, Sung Kyu Lim. 783-788 [doi]
• Flexible 2D layout decomposition framework for spacer-type double pattering lithographyYongchan Ban, Kevin Lucas, David Z. Pan. 789-794 [doi]
• AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detectionDuo Ding, Jhih-Rong Gao, Kun Yuan, David Z. Pan. 795-800 [doi]
• A fast solver for nonlocal electrostatic theory in biomolecular science and engineeringJaydeep P. Bardhan, Andreas Hildebrandt. 801-805 [doi]
• Biochemical oscillator sensitivity analysis in the presence of conservation constraintsJared E. Toettcher, Anya Castillo, Bruce Tidor, Jacob White. 806-811 [doi]
• In silico synchronization of cellular populations through expression data deconvolutionMarisa Eisenberg, Joshua N. Ash, Dan Siegal-Gaskins. 812-817 [doi]
• MO-pack: many-objective clustering for FPGA CADSenthilkumar Thoravi Rajavel, Ali Akoglu. 818-823 [doi]
• Enforcing architectural contracts in high-level synthesisNikhil A. Patil, Ankit Bansal, Derek Chiou. 824-829 [doi]
• Shared reconfigurable fabric for multi-core customizationLiang Chen, Tulika Mitra. 830-835 [doi]
• Synchronous sequential computation with molecular reactionsHua Jiang, Marc D. Riedel, Keshab K. Parhi. 836-841 [doi]
• Facing the challenge of new design features: an effective verification approachWisam Kadry, Ronny Morad, Alex Goryachev, Eli Almog, Christopher A. Krygowski. 842-847 [doi]
• Learning microarchitectural behaviors to improve stimuli generation qualityYoav Katz, Michal Rimon, Avi Ziv, Gai Shaked. 848-853 [doi]
• Robust partitioning for hardware-accelerated functional verificationMichael D. Moffitt, Mátyás A. Sustik, Paul G. Villarrubia. 854-859 [doi]
• Threadmill: a post-silicon exerciser for multi-threaded processorsAllon Adir, Maxim Golubev, Shimon Landa, Amir Nahir, Gil Shurek, Vitali Sokhin, Avi Ziv. 860-865 [doi]
• CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variationsChun-Yi Lee, Niraj K. Jha. 866-871 [doi]
• A case for NEMS-based functional-unit power gating of low-power embedded microprocessorsMichael B. Henry, Meeta Srivastav, Leyla Nazhandali. 872-877 [doi]
• Automated mapping for reconfigurable single-electron transistor arraysYung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan. 878-883 [doi]
• Universal logic modules based on double-gate carbon nanotube transistorsAndrew Zukoski, Xuebei Yang, Kartik Mohanram. 884-889 [doi]
• Virtualization of heterogeneous machines hardware description in a synthesizable object-oriented languageJoshua S. Auerbach, David F. Bacon, Perry Cheng, Rodric M. Rabbah, Sunil Shukla. 890-894 [doi]
• Process-level virtualization for runtime adaptation of embedded softwareKim M. Hazelwood. 895-900 [doi]
• Virtualizing embedded systems: why bother?Gernot Heiser. 901-905 [doi]
• Virtualizing real-time embedded systems with JavaJan Vitek. 906-911 [doi]
• DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chipsAndrew DeOrio, Konstantinos Aisopos, Valeria Bertacco, Li-Shiuan Peh. 912-917 [doi]
• A fault-tolerant NoC scheme using bidirectional channelWen-Chung Tsai, Deng-Yuan Zheng, Sao-Jie Chen, Yu Hen Hu. 918-923 [doi]
• Process variation-aware routing in NoC based multicoresAkbar Sharifi, Mahmut T. Kandemir. 924-929 [doi]
• Enabling system-level modeling of variation-induced faults in networks-on-chipsKonstantinos Aisopos, Chia-Hsin Owen Chen, Li-Shiuan Peh. 930-935 [doi]
• FlexiBuffer: reducing leakage power in on-chip network routersGwangsun Kim, John Kim, Sungjoo Yoo. 936-941 [doi]
• Capacity optimized NoC for multi-mode SoCIsask'har Walter, Erez Kantor, Israel Cidon, Shay Kutten. 942-947 [doi]
• Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systemsWeixun Wang, Prabhat Mishra, Sanjay Ranka. 948-953 [doi]
• A helper thread based dynamic cache partitioning scheme for multithreaded applicationsMahmut T. Kandemir, Taylan Yemliha, Emre Kultursay. 954-959 [doi]
• A reuse-aware prefetching scheme for scratchpad memoryJason Cong, Hui Huang 0001, Chunyue Liu, Yi Zou. 960-965 [doi]
• Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platformsCarlos Flores Fajardo, Zhen Fang, Ravi Iyer, German Fabila Garcia, Seung Eun Lee, Li Zhao. 966-971 [doi]
• Wear rate leveling: lifetime enhancement of PRAM with endurance variationJianbo Dong, Lei Zhang 0008, Yinhe Han, Ying Wang, Xiaowei Li 0001. 972-977 [doi]
• Matching cache access behavior and bit error pattern for high performance low Vcc L1 cacheYoung-Geun Choi, Sungjoo Yoo, Sunggu Lee, Jung Ho Ahn. 978-983 [doi]
• DDmin) of CMOS logic gatesHiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. 984-989 [doi]
• Pipeline strategy for improving optimal energy efficiency in ultra-low voltage designMingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester. 990-995 [doi]
• IR voltage drop analysis exploiting localitySelçuk Köse, Eby G. Friedman. 996-1001 [doi]
• Decoupling for power gating: sources of power noise and design strategiesTong Xu, Peng Li, Boyuan Yan. 1002-1007 [doi]
• Error-resilient low-power DSP via path-delay shapingPaul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh. 1008-1013 [doi]
• Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell libraryAlessandro Cevrero, Francesco Regazzoni, Micheal Schwander, Stéphane Badel, Paolo Ienne, Yusuf Leblebici. 1014-1019 [doi]
• EFFEX: an embedded processor for computer vision based feature extractionJason Clemons, Andrew Jones, Robert Perricone, Silvio Savarese, Todd M. Austin. 1020-1025 [doi]
• Run-time adaptive energy-aware motion and disparity estimation in multiview video codingBruno Zatt, Muhammad Shafique, Felipe Sampaio, Luciano Volcan Agostini, Sergio Bampi, Jörg Henkel. 1026-1031 [doi]
• Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case studyHaris Javaid, Muhammad Shafique, Sri Parameswaran, Jörg Henkel. 1032-1037 [doi]
• RJOP: a customized Java processor for reactive embedded systemsMuhammad Nadeem, Morteza Biglari-Abhari, Zoran Salcic. 1038-1043 [doi]
• Hermes: an integrated CPU/GPU microarchitecture for IP routingYuhao Zhu, Yangdong Deng, Yubei Chen. 1044-1049 [doi]
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