Abstract is missing.
- Robust design of power-efficient VLSI circuitsMassoud Pedram. 1-2 [doi]
- Professor Ernest Kuh s talkErnest S. Kuh. 3-4 [doi]
- Placement and beyond in honor of Ernest S. KuhChung-Kuan Cheng. 5-8 [doi]
- From academic ideas to practical physical design toolsRen-Song Tsay. 9-12 [doi]
- On old and new routing problemsMalgorzata Marek-Sadowska. 13-20 [doi]
- Grid-to-ports clock routing for high performance microprocessor designsHaitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, C. N. Sze. 21-28 [doi]
- Cross link insertion for improving tolerance to variations in clock network synthesisTarun Mittal, Cheng-Kok Koh. 29-36 [doi]
- Synthesis of low power clock trees for handling power-supply variationsShashank Bujimalla, Cheng-Kok Koh. 37-44 [doi]
- RegularRoute: an efficient detailed router with regular routing patternsYanheng Zhang, Chris Chu. 45-52 [doi]
- An enhanced global router with consideration of general layer directivesTsung-Hsien Lee, Yen-Jung Chang, Ting-Chi Wang. 53-60 [doi]
- Obstacle-aware length-matching bus routingJin-Tai Yan, Zhi-Wei Chen. 61-68 [doi]
- Co-optimization of droplet routing and pin assignment in disposable digital microfluidic biochipsYang Zhao, Krishnendu Chakrabarty. 69-76 [doi]
- 3DICs for tera-scale computing: a case studyTanay Karnik, Dinesh Somasekhar, Shekhar Borkar. 77-78 [doi]
- Advances in 3D integrated circuitsRobert Patti. 79-80 [doi]
- Assembling 2D blocks into 3D chipsJohann Knechtel, Igor L. Markov, Jens Lienig. 81-88 [doi]
- Automated placement for custom digital designsTung-Chieh Chen. 89-90 [doi]
- Quantifying academic placer performance on custom designsSamuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl Swartzlander. 91-98 [doi]
- Regularity-constrained floorplanning for multi-core processorsXi Chen, Jiang Hu, Ning Xu. 99-106 [doi]
- Power-driven flip-flop merging and relocationShao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak. 107-114 [doi]
- INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphsIris Hui-Ru Jiang, Chih-Long Chang, Yu-Ming Yang, Evan Y.-W. Tsai, Lancer S.-F. Chen. 115-122 [doi]
- Obstacle-aware clock-tree shaping during placementDongJin Lee, Igor L. Markov. 123-130 [doi]
- Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesisJianchao Lu, Xiaomi Mao, Baris Taskin. 131-138 [doi]
- Impact of manufacturing on routing methodology at 32/22 nmAlexander Volkov. 139-140 [doi]
- The ISPD-2011 routability-driven placement contest and benchmark suiteNatarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Gi-Joon Nam, Jarrod A. Roy. 141-146 [doi]
- Vertical slit transistor based integrated circuits (veSTICs): feasibility studyWojciech Maly. 147-148 [doi]
- Litho and design: moore close than everVivek Singh. 149-150 [doi]
- E-beam lithography stencil planning and optimization with overlapped charactersKun Yuan, David Z. Pan. 151-158 [doi]
- More realistic power grid verification based on hierarchical current and power constraintsChung-Kuan Cheng, Peng Du, Andrew B. Kahng, Grantham K. H. Pang, Yuanzhe Wang, Ngai Wong. 159-166 [doi]
- Lagrangian relaxation for gate implementation selectionYi-Le Huang, Jiang Hu, Weiping Shi. 167-174 [doi]
- Stochastic analog circuit behavior modeling by point estimation methodFang Gong, Hao Yu, Lei He. 175-182 [doi]