Abstract is missing.
- All things are connectedAlberto L. Sangiovanni-Vincentelli. 1 [doi]
- Wireless communication - successful differentiation on standard technology by innovationHermann Eul. 2 [doi]
- Loosely Time-Triggered Architectures for Cyber-Physical SystemsAlbert Benveniste. 3-8 [doi]
- Energy-efficient real-time task scheduling with temperature-dependent leakageChuan-Yue Yang, Jian-Jia Chen, Lothar Thiele, Tei-Wei Kuo. 9-14 [doi]
- Predicting energy and performance overhead of Real-Time Operating SystemsSandro Penolazzi, Ingo Sander, Ahmed Hemani. 15-20 [doi]
- Temperature-aware idle time distribution for energy optimization with dynamic voltage scalingMin Bao, Alexandru Andrei, Petru Eles, Zebo Peng. 21-26 [doi]
- Multicore soft error rate stabilization using adaptive dual modular redundancyRamakrishna Vadlamani, Jia Zhao, Wayne P. Burleson, Russell Tessier. 27-32 [doi]
- A fully-asynchronous low-power framework for GALS NoC integrationYvain Thonnart, Pascal Vivet, Fabien Clermidy. 33-38 [doi]
- Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controllerXiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen. 39-44 [doi]
- MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architectureSergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Rostagno, Maurizio Zamboni. 45-50 [doi]
- AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCsLin Huang, Qiang Xu. 51-56 [doi]
- Statistical SRAM analysis for yield enhancementPaul Zuber, Miguel Miranda, Petr Dobrovolný, Koen van der Zanden, Jong-Hoon Jung. 57-62 [doi]
- Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test schemeMingjing Chen, Alex Orailoglu. 63-68 [doi]
- Scan based methodology for reliable state retention power gating designsSheng Yang, Bashir M. Al-Hashimi, David Flynn, S. Saqib Khursheed. 69-74 [doi]
- TLM+ modeling of embedded HW/SW systemsWolfgang Ecker, Volkan Esen, Robert Schwencker, Thomas Steininger, Michael Velten. 75-80 [doi]
- Scenario extraction for a refined timing-analysis of automotive network topologiesMatthias Traub, Thilo Streichert, Oleg Krasovytskyy, Jürgen Becker. 81-86 [doi]
- Graphical Model Debugger Framework for embedded systemsKebin Zeng, Yu Guo, Christo Angelov. 87-92 [doi]
- IP routing processing with graphic processorsShuai Mu, Xinya Zhang, Nairen Zhang, Jiaxin Lu, Yangdong Steve Deng, Shu Zhang. 93-98 [doi]
- An efficient distributed memory interface for many-core platform with 3D stacked DRAMIgor Loi, Luca Benini. 99-104 [doi]
- Efficient OpenMP data mapping for multicore platforms with vertically stacked memoryAndrea Marongiu, Martino Ruggiero, Luca Benini. 105-110 [doi]
- Energy-efficient variable-flow liquid cooling in 3D stacked architecturesAyse Kivilcim Coskun, David Atienza, Tajana Simunic Rosing, Thomas Brunschwiler, Bruno Michel. 111-116 [doi]
- Optimization of an on-chip active cooling system based on thin-film thermoelectric coolersJieyi Long, Seda Ogrenci Memik, Matthew Grayson. 117-122 [doi]
- Are we there yet? Has IP block assembly become as easy as LEGO?Bryon Moyer, Joachim Kunkel, John Cornish, Chris Rowen, Eshel Haritan, Yankin Tanurhan. 123 [doi]
- Temperature-aware dynamic resource provisioning in a power-optimized datacenterEhsan Pakbaznia, Mohammad Ghasemazar, Massoud Pedram. 124-129 [doi]
- From transistors to MEMS: Throughput-aware power gating in CMOS circuitsMichael B. Henry, Leyla Nazhandali. 130-135 [doi]
- Energy- and endurance-aware design of phase change memory cachesYongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun, Naehyuck Chang, Yuan Xie. 136-141 [doi]
- Evaluation and design exploration of solar harvested-energy prediction algorithmMustafa Imran Ali, Bashir M. Al-Hashimi, Joaquín Recas, David Atienza. 142-147 [doi]
- A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM)Yiran Chen, Hai Li, XiaoBin Wang, Wenzhong Zhu, Wei Xu, Tong Zhang. 148-153 [doi]
- Pseudo-CMOS: A novel design style for flexible electronicsTsung-Ching Huang, Kenjiro Fukuda, Chun-Ming Lo, Yung-Hui Yeh, Tsuyoshi Sekitani, Takao Someya, Kwang-Ting Cheng. 154-159 [doi]
- Spinto: High-performance energy minimization in spin glassesHéctor J. Garcia, Igor L. Markov. 160-165 [doi]
- TSV redundancy: Architecture and design issues in 3D ICAng-Chih Hsieh, TingTing Hwang, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li. 166-171 [doi]
- A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matchingAditi Rathi, Michael DeBole, Weina Ge, Robert T. Collins, Narayanan Vijaykrishnan. 172-177 [doi]
- Parallel subdivision surface rendering and animation on the Cell BE processorR. Grottesi, S. Morigi, Martino Ruggiero, Luca Benini. 178-183 [doi]
- Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modemCamille Jalier, Didier Lattard, Ahmed Amine Jerraya, Gilles Sassatelli, Pascal Benoit, Lionel Torres. 184-189 [doi]
- Recursion-driven parallel code generation for multi-core platformsRebecca L. Collins, Bharadwaj Vellore, Luca P. Carloni. 190-195 [doi]
- An industrial design space exploration framework for supporting run-time resource management on multi-core systemsGiovanni Mariani, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria. 196-201 [doi]
- Stretching the limits of FPGA SerDes for enhanced ATE performanceA. M. Majid, David C. Keezer. 202-207 [doi]
- Multi-temperature testing for core-based system-on-chipZhiyuan He, Zebo Peng, Petru Eles. 208-213 [doi]
- Memory testing with a RISC microcontrollerA. J. van de Goor, Georgi Gaydadjiev, Said Hamdioui. 214-219 [doi]
- Constant-time admission control for Deadline Monotonic tasksAlejandro Masrur, Samarjit Chakraborty, Georg Färber. 220-225 [doi]
- Exploiting inter-event stream correlations between output event streams of non-preemptively scheduled tasksJonas Rox, Rolf Ernst. 226-231 [doi]
- Transition-aware real-time task scheduling for reconfigurable embedded systemsHessam Kooti, Elaheh Bozorgzadeh, Shenghui Liao, Lichun Bao. 232-237 [doi]
- IVF: Characterizing the vulnerability of microprocessor structures to intermittent faultsSongjun Pan, Yu Hu, Xiaowei Li. 238-243 [doi]
- Aging-resilient design of pipelined architectures using novel detection and correction circuitsHamed F. Dadgour, Kaustav Banerjee. 244-249 [doi]
- An integrated framework for joint design space exploration of microarchitecture and circuitsOmid Azizi, Aqeel Mahesri, John P. Stevenson, Sanjay J. Patel, Mark Horowitz. 250-255 [doi]
- Challenges in the design of automotive softwareSimon Fürst. 256-258 [doi]
- AUTOSAR and the automotive tool chainStefan Voget. 259-262 [doi]
- High-fidelity markovian power model for protocolsJing Cao, Albert Nymeyer. 267-270 [doi]
- Energy-performance design space exploration in SMT architectures exploiting selective load value predictionsArpad Gellert, Gianluca Palermo, Vittorio Zaccaria, Adrian Florea, Lucian N. Vintan, Cristina Silvano. 271-274 [doi]
- Error resilience of intra-die and inter-die communication with 3D spidergon STNoCVladimir Pasca, Lorena Anghel, Claudia Rusu, Riccardo Locatelli, Massimo Coppola. 275-278 [doi]
- Towards a chip level reliability simulator for copper/low-k backend processesMuhammad Bashir, Linda S. Milor. 279-282 [doi]
- NBTI modeling in the framework of temperature variationSeyab, Said Hamdioui. 283-286 [doi]
- RunAssert: A non-intrusive run-time assertion for parallel programs debuggingChi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Tay-Jyi Lin. 287-290 [doi]
- An RDL-configurable 3D memory tier to replace on-chip SRAMMarco Facchini, Paul Marchal, Francky Catthoor, Wim Dehaene. 291-294 [doi]
- GentleCool: Cooling aware proactive workload scheduling in multi-machine systemsRaid Ayoub, Shervin Sharifi, Tajana Simunic Rosing. 295-298 [doi]
- Timing modeling for digital sub-threshold circuitsNiklas Lotze, Jacob Göppert, Yiannos Manoli. 299-302 [doi]
- Power consumption of logic circuits in ambipolar carbon nanotube technologyM. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli. 303-306 [doi]
- Reversible logic synthesis through ant colony optimizationMin Li, Yexin Zheng, Michael S. Hsiao, Chao Huang. 307-310 [doi]
- Low-power FinFET circuit synthesis using surface orientation optimizationPrateek Mishra, Niraj K. Jha. 311-314 [doi]
- Implementing digital logic with sinusoidal suppliesKalyana C. Bollapalli, Sunil P. Khatri, Laszlo B. Kish. 315-318 [doi]
- A reconfigurable multiprocessor architecture for a reliable face recognition implementationAntonino Tumeo, Francesco Regazzoni, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto. 319-322 [doi]
- A systematic approach to the test of combined HW/SW systemsAlexander Krupp, Wolfgang Müller 0003. 323-326 [doi]
- A new approach for adaptive failure diagnostics based on emulation testSteffen Ostendorff, Heinz-Dietrich Wuttke, Jörg Sachße, S. Köhler. 327-330 [doi]
- Integrated end-to-end timing analysis of networked AUTOSAR-compliant systemsKarthik Lakshmanan, Gaurav Bhatia, Ragunathan Rajkumar. 331-334 [doi]
- Scalable stochastic processorsSriram Narayanan, John Sartori, Rakesh Kumar, Douglas L. Jones. 335-338 [doi]
- AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabricsBahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici. 339-344 [doi]
- On the efficacy of write-assist techniques in low voltage nanoscale SRAMsVikas Chandra, Cezary Pietrzyk, Robert C. Aitken. 345-350 [doi]
- Optimizing the power delivery network in dynamically voltage scaled systems with uncertain power mode transition timesHwisung Jung, Massoud Pedram. 351-356 [doi]
- Run-time spatial resource management for real-time applications on heterogeneous MPSoCsTimon D. ter Braak, Philip K. F. Hölzenspies, Jan Kuper, Johann Hurink, Gerard J. M. Smit. 357-362 [doi]
- Rapid runtime estimation methods for pipelined MPSoCsHaris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran. 363-368 [doi]
- Automatic workload generation for system-level exploration based on modified GCC compilerJari Kreku, Kari Tiensyrjä, Geert Vanmeerbeeck. 369-374 [doi]
- A rapid prototyping system for error-resilient multi-processor systems-on-chipMatthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich. 375-380 [doi]
- Learning-based adaptation to applications and environments in a reconfigurable Network-on-ChipJih-Sheng Shen, Chun-Hsian Huang, Pao-Ann Hsiung. 381-386 [doi]
- Application-specific memory performance of a heterogeneous reconfigurable architectureSean Whitty, Henning Sahlbach, Brady Hurlburt, Rolf Ernst, Wolfram Putzke-Röming. 387-392 [doi]
- A reconfigurable hardware for one bit transform based multiple reference frame Motion EstimationAbdulkadir Akin, G. Sayilar, Ilker Hamzaoglu. 393-398 [doi]
- Ultra-high throughput string matching for Deep Packet InspectionAlan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu. 399-404 [doi]
- A HMMER hardware accelerator using divergencesJuan Fernando Eusse Giraldo, Nahri Moreano, Ricardo Pezzuol Jacobi, Alba Cristina Magalhaes Alves de Melo. 405-410 [doi]
- Proactive NBTI mitigation for busy functional units in out-of-order microprocessorsLin Li, Youtao Zhang, Jun Yang 0002, Jianhua Zhao. 411-416 [doi]
- Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variabilityShrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio. 417-422 [doi]
- Analytical model for TDDB-based performance degradation in combinational logicMihir Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken. 423-428 [doi]
- Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMsBartomeu Alorda, Gabriel Torrens, Sebastiàn A. Bota, Jaume Segura. 429-434 [doi]
- Test front loading in early stages of automotive software development based on AUTOSARAlexander Michailidis, Uwe Spieth, Thomas Ringler, Bernd Hedenetz, Stefan Kowalewski. 435-440 [doi]
- A proposal for real-time interfaces in SPEEDSPurandar Bhaduri, Ingo Stierand. 441-446 [doi]
- Scenario-based analysis and synthesis of real-time systems using uppaalKim Guldstrand Larsen, Shuhao Li, Brian Nielsen, Saulius Pusinskas. 447-452 [doi]
- Variation-aware interconnect extraction using statistical moment preserving model order reductionTarek A. El-Moselhy, Luca Daniel. 453-458 [doi]
- Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrateNavin Srivastava, Roberto Suaya, Kaustav Banerjee. 459-464 [doi]
- HORUS - high-dimensional Model Order Reduction via low moment-matching upgraded samplingJorge Fernandez Villena, Luis Miguel Silveira. 465-470 [doi]
- On passivity of the super node algorithm for EM modeling of interconnect systemsMaria V. Ugryumova, Wil H. A. Schilders. 471-476 [doi]
- Vacuity analysis for property qualification by mutation of checkersLuidi Di Guglielmo, Franco Fummi, Graziano Pravadelli. 478-483 [doi]
- An abstraction-guided simulation approach using Markov models for microprocessor verificationTao Zhang, Tao Lv, Xiaowei Li. 484-489 [doi]
- Efficient decision ordering techniques for SAT-based test generationMingsong Chen, Xiaoke Qin, Prabhat Mishra. 490-495 [doi]
- DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policyMohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran. 496-501 [doi]
- FlashPower: A detailed power model for NAND flash memoryVidyabhushan Mohan, Sudhanva Gurumurthi, Mircea R. Stan. 502-507 [doi]
- A power optimization method for CMOS Op-Amps using sub-space based geometric programmingWei Gao, Richard Hornsey. 508-513 [doi]
- Power gating design for standard-cell-like structured ASICsSin-Yu Chen, Rung-Bin Lin, Hui-Hsiang Tung, Kuen-Wey Lin. 514-519 [doi]
- Dual-Vth leakage reduction with Fast Clock Skew Scheduling EnhancementMeng Tie, Haiying Dong, Tong Wang, Xu Cheng. 520-525 [doi]
- An high voltage CMOS voltage regulator for automotive alternators with programmable functionalities and full reverse polarity capabilityLuca Fanucci, Giuseppe Pasetti, P. D Abramo, R. Serventi, F. Tinfena, P. Chassard, L. Labiste, P. Tisserand. 526-531 [doi]
- Design of an automotive traffic sign recognition system targeting a multi-core SoC implementationMatthias Müller, Axel G. Braun, Joachim Gerlach, Wolfgang Rosenstiel, Dennis Nienhüser, Johann Marius Zöllner, Oliver Bringmann. 532-537 [doi]
- Simulation-based verification of the MOST NetInterface specification revision 3.0Andreas Braun, Oliver Bringmann, Djones Lettnin, Wolfgang Rosenstiel. 538-543 [doi]
- Holistic simulation of FlexRay networks by using run-time model switchingMichael Karner, Eric Armengaud, Christian Steger, Reinhold Weiss. 544-549 [doi]
- Computing robustness of FlexRay schedules to uncertainties in design parametersArkadeb Ghosal, Haibo Zeng, Marco Di Natale, Yakov Ben-Haim. 550-555 [doi]
- Adapting to adaptive testingErik Jan Marinissen, Adit Singh, Dan Glotter, Marco Esposito, John M. Carulli Jr., Amit Nahar, Kenneth M. Butler, Davide Appello, Chris Portelli. 556-561 [doi]
- Using filesystem virtualization to avoid metadata bottlenecksErnest Artiaga, Toni Cortes. 562-567 [doi]
- An accurate system architecture refinement methodology with mixed abstraction-level virtual platformZhe-Mao Hsu, Jen-Chieh Yeh, I-Yao Chuang. 568-573 [doi]
- Non-intrusive virtualization management using libvirtMatthias Bolte, Michael Sievers, Georg Birkenheuer, Oliver Niehorster, André Brinkmann. 574-579 [doi]
- Process variation and temperature-aware reliability managementCheng Zhuo, Dennis Sylvester, David Blaauw. 580-585 [doi]
- Optimized self-tuning for circuit agingEvelyn Mintarno, Joelle Skaf, Rui Zheng, Jyothi Velamala, Yu Cao, Stephen P. Boyd, Robert W. Dutton, Subhasish Mitra. 586-591 [doi]
- Investigating the impact of NBTI on different power saving cache strategiesAndrew J. Ricketts, J. Singh, Krishnan Ramakrishnan, Narayanan Vijaykrishnan, D. K. Pradhan. 592-597 [doi]
- Energy-oriented dynamic SPM allocation based on time-slotted Cache conflict graphWang Huan, Zhang Yang, Mei Chen, Ling Ming. 598-601 [doi]
- Enhanced Q-learning algorithm for dynamic power management with performance constraintWei Liu, Ying Tan, Qinru Qiu. 602-605 [doi]
- Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstationsAline Mello, Isaac Maia, Alain Greiner, François Pêcheux. 606-609 [doi]
- High-speed clock recovery for low-cost FPGAsIstván Haller, Zoltan Francisc Baruch. 610-613 [doi]
- Demonstration of an in-band reconfiguration data distribution and network node reconfigurationUwe Proß, Sebastian Goller, Erik Markert, Michael Jüttner, Jan Langer, Ulrich Heinkel, Joachim Knäblein, Axel Schneider. 614-617 [doi]
- Programmable aging sensor for automotive safety-critical applicationsJulio César Vázquez, Víctor H. Champac, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira. 618-621 [doi]
- Passive reduced order modeling of multiport interconnects via semidefinite programmingZohaib Mahmood, Bradley N. Bond, Tarek Moselhy, Alexandre Megretski, Luca Daniel. 622-625 [doi]
- GoldMine: Automatic assertion generation using data mining and static analysisShobha Vasudevan, David Sheridan, Sanjay J. Patel, David Tcheng, William Tuohy, Daniel R. Johnson. 626-629 [doi]
- Assertion-based verification of RTOS propertiesMarcio F. S. Oliveira, Henning Zabel, Wolfgang Müller 0003. 630-633 [doi]
- Post-placement temperature reduction techniquesWei Liu, Alberto Nannarelli, Andrea Calimera, Enrico Macii, Massimo Poncino. 634-637 [doi]
- Clock gating approaches by IOEX graphs and cluster efficiency plotsJithendra Srinivas, Sukumar Jairam. 638-641 [doi]
- Timing modeling and analysis for AUTOSAR-based software development - a case studyKay Klobedanz, Christoph Kuznik, Andreas Thuy, Wolfgang Müller 0003. 642-645 [doi]
- Design of a real-time optimized emulation methodTimo Kerstan, Markus Oertel. 646-649 [doi]
- Capturing intrinsic parameter fluctuations using the PSP compact modelBinjie Cheng, Daryoosh Dideban, Negin Moezi, Campbell Millar, Gareth Roy, Xingsheng Wang, Scott Roy, Asen Asenov. 650-653 [doi]
- Power efficient voltage islanding for Systems-on-chip from a floorplanning perspectivePavel Ghosh, Arunabha Sen. 654-657 [doi]
- Always energy-optimal microscopic wireless systemsJan M. Rabaey. 658 [doi]
- Hardware / software design challenges of low-power sensor nodes for condition monitoringHendrik Ahlendorf, Lars Gopfert. 659 [doi]
- Monolithically stackable hybrid FPGADmitri Strukov, Alan Mishchenko. 661-666 [doi]
- Spintronic memristor devices and applicationXiaoBin Wang, Yiran Chen. 667-672 [doi]
- Compact model of memristors and its application in computing systemsHai Li, Miao Hu. 673-678 [doi]
- Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCsDaniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev, Luca Benini, Davide Bertozzi. 679-684 [doi]
- A methodology for the characterization of process variation in NoC linksCarles Hernandez, Federico Silla, José Duato. 685-690 [doi]
- PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networksJohnnie Chan, Gilbert Hendry, Aleksandr Biberman, Keren Bergman, Luca P. Carloni. 691-696 [doi]
- An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operationArnd Geis, Pierluigi Nuzzo, Julien Ryckaert, Yves Rolainy, Gerd Vandersteeny, Jan Craninckx. 697-701 [doi]
- A compact digital amplitude modulator in 90nm CMOSV. Chironi, Björn Debaillie, Andrea Baschirotto, Jan Craninckx, M. Ingels. 702-705 [doi]
- A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDRThomas Froehlich, Vivek Sharma, Markus Bingesser. 706-710 [doi]
- Ultra-low power mixed-signal design platform using subthreshold source-coupled circuitsArmin Tajalli, Yusuf Leblebici. 711-716 [doi]
- Clock skew scheduling for soft-error-tolerant sequential circuitsKai-Chiang Wu, Diana Marculescu. 717-722 [doi]
- HW/SW co-detection of transient and permanent faults with fast recovery in statically scheduled data pathsMario Schölzel. 723-728 [doi]
- Scalable codeword generation for coupled busesKedar Karmarkar, Spyros Tragoudas. 729-734 [doi]
- An adaptive code rate EDAC scheme for random access memoryChing-Yi Chen, Cheng-Wen Wu. 735-740 [doi]
- Worst case delay analysis for memory interference in multicore systemsRodolfo Pellizzoni, Andreas Schranzhofer, Jian-Jia Chen, Marco Caccamo, Lothar Thiele. 741-746 [doi]
- Throughput modeling to evaluate process merging transformations in polyhedral process networksSjoerd Meijer, Hristo Nikolov, Todor Stefanov. 747-752 [doi]
- Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platformsJerónimo Castrillón, Ricardo Velasquez, Anastasia Stulova, Weihua Sheng, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 753-758 [doi]
- Bounding the shared resource load for the performance analysis of multiprocessor systemsSimon Schliecker, Mircea Negrean, Rolf Ernst. 759-764 [doi]
- An error-correcting unordered code and hardware support for robust asynchronous global communicationMelinda Y. Agyekum, Steven M. Nowick. 765-770 [doi]
- Large-scale Boolean matchingHadi Katebi, Igor L. Markov. 771-776 [doi]
- KL-Cuts: A new approach for logic synthesis targeting multiple output blocksOsvaldo Martinello, Felipe S. Marques, Renato P. Ribas, André Inácio Reis. 777-782 [doi]
- RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applicationsSamuel B. Luckenbill, Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He. 783-788 [doi]
- Panel 6.8: The challenges of heterogeneous multicore debugGrant Martin, Albrecht Mayer. 789 [doi]
- Why design must change: Rethinking digital designMark Horowitz. 791 [doi]
- Low power design of the X-GOLD:::®::: SDR 20 baseband processorWolfgang Raab, Jörg Berthold, J. A. Ulrich Hachmann, Dominik Langen, Michael Schreiner, Holger Eisenreich, Jens-Uwe Schluessler, Georg Ellguth. 792-793 [doi]
- Low power mobile internet devices using LTE technologyVolker Aue. 794 [doi]
- A black box method for stability analysis of arbitrary SRAM cell structuresMichael Wieckowski, Dennis Sylvester, David Blaauw, Vikas Chandra, Sachin Idgunji, Cezary Pietrzyk, Robert C. Aitken. 795-800 [doi]
- Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysisMasood Qazi, Mehul Tikekar, Lara Dolecek, Devavrat Shah, Anantha Chandrakasan. 801-806 [doi]
- Practical Monte-Carlo based timing yield estimation of digital circuitsJavid Jaffari, Mohab Anis. 807-812 [doi]
- Statistical static timing analysis using Markov chain Monte CarloYashodhan Kanoria, Subhasish Mitra, Andrea Montanari. 813-818 [doi]
- KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architectureRalf König, Lars Bauer, Timo Stripf, Muhammad Shafique, Waheed Ahmed, Jürgen Becker, Jörg Henkel. 819-824 [doi]
- A reconfigurable cache memory with heterogeneous banksDomingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque. 825-830 [doi]
- Evaluation of runtime task mapping heuristics with rSesame - a case studyKamana Sigdel, Mark Thompson, Carlo Galuzzi, Andy D. Pimentel, Koen Bertels. 831-836 [doi]
- VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded SystemsAbelardo Jara-Berrocal, Ann Gordon-Ross. 837-842 [doi]
- pSHS: A scalable parallel software implementation of Montgomery multiplication for multicore systemsZhimin Chen, Patrick Schaumont. 843-848 [doi]
- BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluationMaxime Nassar, Shivam Bhasin, Jean-Luc Danger, Guillaume Duc, Sylvain Guilley. 849-854 [doi]
- Fault-based attack of RSA authenticationAndrea Pellegrini, Valeria Bertacco, Todd M. Austin. 855-860 [doi]
- Detecting/preventing information leakage on the memory bus due to malicious hardwareAbhishek Das, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary. 861-866 [doi]
- An embedded platform for privacy-friendly road charging applicationsJosep Balasch, Ingrid Verbauwhede, Bart Preneel. 867-872 [doi]
- Defect aware X-filling for low-power scan testingS. Balatsouka, V. Tenentes, Xrysovalantis Kavousianos, Krishnendu Chakrabarty. 873-878 [doi]
- Parallel X-fault simulation with critical path tracing techniqueRaimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman. 879-884 [doi]
- Diagnosis of multiple arbitrary faults with mask and reinforcement effectJing Ye, Yu Hu, Xiaowei Li. 885-890 [doi]
- Skewed pipelining for parallel simulink simulationsArquimedes Canedo, Takeo Yoshizawa, Hideaki Komatsu. 891-896 [doi]
- An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platformsAlessio Bonfietti, Luca Benini, Michele Lombardi, Michela Milano. 897-902 [doi]
- A software update service with self-protection capabilitiesMoritz Neukirchner, Steffen Stein, Harald Schrom, Rolf Ernst. 903-908 [doi]
- Bitstream processing for embedded systems using C++ metaprogrammingReimund Klemm, Gerhard Fettweis. 909-913 [doi]
- Increasing PCM main memory lifetimeAlexandre Peixoto Ferreira, Miao Zhou, S. Bock, Bruce R. Childers, Rami G. Melhem, Daniel Mossé. 914-919 [doi]
- Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithmAndhi Janapsatya, Aleksandar Ignjatovic, Jorgen Peddersen, Sri Parameswaran. 920-925 [doi]
- A memory- and time-efficient on-chip TCAM minimizer for IP lookupHeeyeol Yu. 926-931 [doi]
- Panel Session - Who Is Closing the embedded software design gap?Wolfgang Ecker, Pierre Bricaud, Rainer Doemer, Yossi Veller, Stefan Heinen, Jurgen Mossinger, Andreas von Schwerin. 932 [doi]
- Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCsBinzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li. 933-936 [doi]
- A High-Voltage Low-Power DC-DC buck regulator for automotive applicationsGiuseppe Pasetti, Luca Fanucci, R. Serventi. 937-940 [doi]
- SimTag: Exploiting tag bits similarity to improve the reliability of the data cachesJesung Kim, Soontae Kim, Yebin Lee. 941-944 [doi]
- The split register fileJaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera. 945-948 [doi]
- Multithreaded code from synchronous programs: Extracting independent threads for OpenMPDaniel Baudisch, Jens Brandt, Klaus Schneider. 949-952 [doi]
- RMOT: Recursion in model order for task execution time estimation in a software pipelineNabeel Iqbal, M. A. Siddique, Jörg Henkel. 953-956 [doi]
- Approximate logic synthesis for error tolerant applicationsDoochul Shin, Sandeep K. Gupta. 957-960 [doi]
- Automatic microarchitectural pipeliningMarc Galceran Oms, Jordi Cortadella, Dmitry Bufistov, Michael Kishinevsky. 961-964 [doi]
- Non-linear Operating Point Statistical Analysis for Local Variations in logic timing at low voltageRahul Rithe, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha Chandrakasan. 965-968 [doi]
- Dynamically reconfigurable register file for a softcore VLIW processorStephan Wong, Fakhar Anjam, Faisal Nadeem. 969-972 [doi]
- FPGA-based adaptive computing for correlated multi-stream processingMing Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch. 973-976 [doi]
- Far Correlation-based EMA with a precharacterized leakage modelOlivier Meynard, Sylvain Guilley, Jean-Luc Danger, Laurent Sauvage. 977-980 [doi]
- Improved countermeasure against Address-bit DPA for ECC scalar multiplicationMasami Izumi, Jun Ikegami, Kazuo Sakiyama, Kazuo Ohta. 981-984 [doi]
- Enabling efficient post-silicon debug by clustering of hardware-assertionsMohammad Hossein Neishaburi, Zeljko Zilic. 985-988 [doi]
- Constrained Power Management: Application to a multimedia mobile platformPatrick Bellasi, Stefano Bosisio, Matteo Carnevali, William Fornaciari, David Siorpaes. 989-992 [doi]
- Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuitsFarhad Mehdipour, Hiroaki Honda, Hiroshi Kataoka, Koji Inoue, Irina Kataeva, Kazuaki Murakami, Hiroyuki Akaike, Akira Fujimaki. 993-996 [doi]
- MB-LITE: A robust, light-weight soft-core implementation of the MicroBlaze architectureTamar Kranenburg, Rene van Leuken. 997-1000 [doi]
- Automatic pipelining from transactional datapath specificationsEriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu. 1001-1004 [doi]
- Increasing the power efficiency of PCs by improving the hardware/OS interactionChris Schläger. 1005 [doi]
- Optimize your power and performance yields and regain those sleepless nightsKrisztián Flautner. 1006 [doi]
- Digital statistical analysis using VHDLManfred Dietrich, Uwe Eichler, Joachim Haase. 1007-1010 [doi]
- A resilience roadmapSani R. Nassif, Nikil Mehta, Yu Cao. 1011-1016 [doi]
- Vision for cross-layer optimization to address the dual challenges of energy and reliabilityAndré DeHon, Heather M. Quinn, Nicholas P. Carter. 1017-1022 [doi]
- Design techniques for cross-layer resilienceNicholas P. Carter, Helia Naeimi, Donald S. Gardner. 1023-1028 [doi]
- Cross-layer resilience challenges: Metrics and optimizationSubhasish Mitra, Kevin Brelsford, Pia N. Sanda. 1029-1034 [doi]
- Pareto efficient design for reconfigurable streaming applications on CPU/FPGAsJun Zhu, Ingo Sander, Axel Jantsch. 1035-1040 [doi]
- Automated bottleneck-driven design-space exploration of media processing systemsYang Yang, Marc Geilen, Twan Basten, Sander Stuijk, Henk Corporaal. 1041-1046 [doi]
- Using Transaction Level Modeling techniques for wireless sensor network simulationMarkus Damm, Javier Moreno, Jan Haase, Christoph Grimm. 1047-1052 [doi]
- RTOS-aware refinement for TLM2.0-based HW/SW designsMarkus Becker, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller 0003, Graziano Pravadelli, Tao Xie. 1053-1058 [doi]
- Power Variance Analysis breaks a masked ASIC implementation of AESYang Li, Kazuo Sakiyama, Lejla Batina, D. Nakatsu, Kazuo Ohta. 1059-1064 [doi]
- Novel Physical Unclonable Function with process and environmental variationsXiaoxiao Wang, Mohammad Tehranipoor. 1065-1070 [doi]
- Ultra low-power 12-bit SAR ADC for RFID applicationsDaniela De Venuto, Eduard Stikvoort, David Tio Castro, Youri Ponomarev. 1071-1075 [doi]
- A flexible UWB Transmitter for breast cancer detection imaging systemsMassimo Cutrupi, Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano. 1076-1081 [doi]
- A portable multi-pitch e-drum based on printed flexible pressure sensorsChun-Ming Lo, Tsung-Ching Huang, Cheng-Yi Chiang, J. Hou, Kwang-Ting Cheng. 1082-1087 [doi]
- Computation of yield-optimized Pareto fronts for analog integrated circuit specificationsDaniel Mueller-Gritschneder, Helmut Graeb. 1088-1093 [doi]
- Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexityElie Maricau, Georges G. E. Gielen. 1094-1099 [doi]
- A general mathematical model of probabilistic ripple-carry addersMark S. K. Lau, Keck Voon Ling, Yun-Chung Chu, Arun Bhanu. 1100-1105 [doi]
- An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search techniqueBo Liu, Francisco V. Fernández, Georges G. E. Gielen. 1106-1111 [doi]
- Reuse-aware modulo scheduling for stream processorsLi Wang, Jingling Xue, Xuejun Yang. 1112-1117 [doi]
- Compilation of stream programs for multicore processors that incorporate scratchpad memoriesWeijia Che, Amrit Panda, Karam S. Chatha. 1118-1123 [doi]
- Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systemsHideki Takase, Hiroyuki Tomiyama, Hiroaki Takada. 1124-1129 [doi]
- A special-purpose compiler for look-up table and code generation for function evaluationYuanrui Zhang, Lanping Deng, Praveen Yedlapalli, Sai Prashanth Muralidhara, Hui Zhao, Mahmut T. Kandemir, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun. 1130-1135 [doi]
- General behavioral thermal modeling and characterization for multi-core microprocessor designThom Jefferson A. Eguia, Sheldon X.-D. Tan, Ruijing Shen, Eduardo H. Pacheco, Murli Tirumala. 1136-1141 [doi]
- On the construction of guaranteed passive macromodels for high-speed channelsAlessandro Chinea, Stefano Grivet-Talocia, Dirk Deschrijver, Tom Dhaene, Luc Knockaert. 1142-1147 [doi]
- Extended Hamiltonian Pencil for passivity assessment and enforcement for S-parameter systemsZuochang Ye, L. Miguel Silveira, Joel R. Phillips. 1148-1152 [doi]
- Equivalent circuit modeling of multilayered power/ground planes for fast transient simulationTakayuki Watanabe, Hideki Asai. 1153-1158 [doi]
- Carbon nanotube circuits: Living with imperfections and variationsJie Zhang, Nishant Patil, Albert Lin, H.-S. Philip Wong, Subhasish Mitra. 1159-1164 [doi]
- Properties of and improvements to time-domain dynamic thermal analysis algorithmsXi Chen, Robert P. Dick, Li Shang. 1165-1170 [doi]
- Towards assertion-based verification of heterogeneous system designsStefan Lämmermann, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Alexander Viehl, Alexander Jesser, Lars Hedrich. 1171-1176 [doi]
- Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulationMeng-Huan Wu, Wen-Chuan Lee, Chen-Yu Chuang, Ren-Song Tsay. 1177-1182 [doi]
- Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMsRauf Salimi Khaligh, Martin Radetzki. 1183-1188 [doi]
- Efficient High-Level modeling in the networking domainChristian Zebelein, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch. 1189-1194 [doi]
- UML design for dynamically reconfigurable multiprocessor embedded systemsJorgiano Vidal, Florent de Lamotte, Guy Gogniat, Jean-Philippe Diguet, Philippe Soulard. 1195-1200 [doi]
- Closing the gap between UML-based modeling, simulation and synthesis of combined HW/SW systemsFabian Mischkalla, Da He, Wolfgang Müller 0003. 1201-1206 [doi]
- Formal semantics for PSL modeling layer and application to the verification of transactional modelsLuca Ferro, Laurence Pierre. 1207-1212 [doi]
- COTS-based applications in space avionicsMichel Pignol. 1213-1219 [doi]
- Worst-case end-to-end delay analysis of an avionics AFDX networkHenri Bauer, Jean-Luc Scharbarg, Christian Fraboul. 1220-1224 [doi]
- A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAsLuca Sterpone, Niccolò Battezzati. 1231-1236 [doi]
- Reducing the storage requirements of a test sequence by using a background vectorIrith Pomeranz, Sudhakar M. Reddy. 1237-1242 [doi]
- BISD: Scan-based Built-In self-diagnosisMelanie Elm, Hans-Joachim Wunderlich. 1243-1248 [doi]
- Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modulesMohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta. 1249-1254 [doi]
- A generalized control-flow-aware pattern recognition algorithm for behavioral synthesisJason Cong, Hui Huang, Wei Jiang. 1255-1260 [doi]
- Behavioral level dual-vth design for reduced leakage power with thermal awarenessJunbo Yu, Qiang Zhou, Gang Qu, Jinian Bian. 1261-1266 [doi]
- Coordinated resource optimization in behavioral synthesisJason Cong, Bin Liu, Junjuan Xu. 1267-1272 [doi]
- A methodology for propagating design tolerances to shape tolerances for use in manufacturingShayak Banerjee, Kanak B. Agarwal, Chin-Ngai Sze, Sani R. Nassif, Michael Orshansky. 1273-1278 [doi]
- Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidanceXin Gao, Luca Macchiarulo. 1279-1284 [doi]
- Efficient representation, stratification, and compression of variational CSM library waveforms using Robust Principle Component AnalysisSafar Hatami, Massoud Pedram. 1285-1290 [doi]
- Exploiting local logic structures to optimize multi-core SoC floorplanningCheng-Hong Li, Sampada Sonalkar, Luca P. Carloni. 1291-1296 [doi]
- Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systemsSven van Haastregt, Eyal Halm, Bart Kienhuis. 1297-1300 [doi]
- Differential Power Analysis enhancement with statistical preprocessingVictor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres, Michel Robert. 1301-1304 [doi]
- Correlation controlled sampling for efficient variability analysis of analog circuitsJavid Jaffari, Mohab Anis. 1305-1308 [doi]
- Formal verification of analog circuits in the presence of noise and process variationRajeev Narayanan, Behzad Akbarpour, Mohamed H. Zaki, Sofiène Tahar, Lawrence C. Paulson. 1309-1312 [doi]
- Toward optimized code generation through model-based optimizationAsma Charfi, Chokri Mraidha, Sébastien Gérard, François Terrier, Pierre Boulet. 1313-1316 [doi]
- Path-based scheduling in a hardware compilerRuirui Gu, Alessandro Forin, Richard Neil Pittman. 1317-1320 [doi]
- Optimization of FIR filter to improve eye diagram for general transmission line systemsYung-Shou Cheng, Yen-Cheng Lai, Ruey-Beei Wu. 1321-1324 [doi]
- On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated CircuitsRoshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen. 1325-1328 [doi]
- Interconnect delay and slew metrics using the beta distributionJun-Kuei Zeng, Chung-Ping Chen. 1329-1332 [doi]
- Accurate timed RTOS model for transaction level modelingYonghyun Hwang, Gunar Schirner, Samar Abdi, Daniel D. Gajski. 1333-1336 [doi]
- A modeling method by eliminating execution traces for performance evaluationKouichi Ono, Manabu Toyota, Ryo Kawahara, Yoshifumi Sakamoto, Takeo Nakada, Naoaki Fukuoka. 1337-1340 [doi]
- Verifying UML/OCL models using Boolean satisfiabilityMathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler. 1341-1344 [doi]
- High temperature polymer capacitors for aerospace applicationsClinton K. Landrock, Bozena Kaminska. 1349-1352 [doi]
- An on-chip clock generation scheme for faster-than-at-speed delay testingSongwei Pei, Huawei Li, Xiaowei Li. 1353-1356 [doi]
- Construction of dual mode components for reconfiguration aware high-level synthesisGeorge Economakos, Sotirios Xydis, Ioannis Koutras, Dimitrios Soudris. 1357-1360 [doi]
- Optimizing Data-Flow Graphs with min/max, adding and relational operationsJ. Perez, P. Sanchez, V. Fernandez. 1361-1364 [doi]
- Optimization of the bias current network for accurate on-chip thermal monitoringJieyi Long, Seda Ogrenci Memik. 1365-1368 [doi]
- SAT based multi-net rip-up-and-reroute for manufacturing hotspot removalFan Yang, Yici Cai, Qiang Zhou, Jiang Hu. 1369-1372 [doi]
- NIM- a noise index model to estimate delay discrepancies between silicon and simulationElif Alpaslan, Jennifer Dworak, Bram Kruseman, Ananta K. Majhi, Wilmar M. Heuvelman, Paul van de Wiel. 1373-1376 [doi]
- Panel: First commandment at least, do nothing well!Marco Casale-Rossi, Giovanni De Micheli, Antun Domic, Enrico Macii, Piero Perlo, Andreas Wild, Roberto Zafalon. 1377 [doi]
- SigNet: Network-on-chip filtering for coarse vector directoriesNatalie D. Enright Jerger. 1378-1383 [doi]
- Feedback control for providing QoS in NoC based multicoresAkbar Sharifi, Hui Zhao, Mahmut T. Kandemir. 1384-1389 [doi]
- Exploiting multiple switch libraries in topology synthesis of on-chip interconnection networkMinje Jun, Sungroh Yoon, Eui-Young Chung. 1390-1395 [doi]
- Low-complexity high throughput VLSI architecture of soft-output ML MIMO detectorTeo Cupaiuolo, Massimiliano Siti, Alessandro Tomasoni. 1396-1401 [doi]
- A low cost multi-standard near-optimal soft-output sphere decoder: Algorithm and architectureÖzgün Paker, Sebastian Eckert, Andreas Bury. 1402-1407 [doi]
- Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case studyRudy Beraha, Isask har Walter, Israel Cidon, Avinoam Kolodny. 1408-1413 [doi]
- Domain specific architecture for next generation wireless communicationBotao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo, Ting Chen. 1414-1419 [doi]
- A 150Mbit/s 3GPP LTE Turbo code decoderMatthias May, Thomas Ilnseher, Norbert Wehn, Wolfgang Raab. 1420-1425 [doi]
- High-quality pattern selection for screening small-delay defects considering process variations and crosstalkKe Peng, Mahmut Yilmaz, Mohammad Tehranipoor, Krishnendu Chakrabarty. 1426-1431 [doi]
- Layout-aware pseudo-functional testing for critical paths considering power supply noise effectsXiao Liu, Yubin Zhang, Feng Yuan, Qiang Xu. 1432-1437 [doi]
- On reset based functional broadside testsIrith Pomeranz, Sudhakar M. Reddy. 1438-1443 [doi]
- Scheduling for energy efficiency and fault tolerance in hard real-time systemsYu Liu, Han Liang, Kaijie Wu. 1444-1449 [doi]
- Scoped identifiers for efficient bit aligned loggingRoy Shea, Mani B. Srivastava, Young Cho. 1450-1455 [doi]
- Linear programming approach for performance-driven data aggregation in networks of embedded sensorsCristian Ferent, Varun Subramanian, Michael Gilberti, Alex Doboli. 1456-1461 [doi]
- Soft error-aware design optimization of low power and time-constrained embedded systemsRishad A. Shafik, Bashir M. Al-Hashimi, Krishnendu Chakrabarty. 1462-1467 [doi]
- Contango: Integrated optimization of SoC clock networksDongJin Lee, Igor L. Markov. 1468-1473 [doi]
- Clock skew optimization considering complicated power modesChiao-Ling Lung, Zi-Yi Zeng, Chung-Han Chou, Shih-Chieh Chang. 1474-1479 [doi]
- A general method to make multi-clock system deterministicMenghao Su, Yunji Chen, Xiang Gao. 1480-1485 [doi]
- Embedded software testing: What kind of problem is this?Érika F. Cota. 1486 [doi]
- Nanoelectronics challenges for the 21:::st::: centuryDimitri Antoniadis. 1487 [doi]
- Cool MPSoC programmingRainer Leupers, Lothar Thiele, Xiaoning Nie, Bart Kienhuis, Matthias Weiss, Tsuyoshi Isshiki. 1488-1493 [doi]
- Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case studyHong-Zu Chou, Haiqian Yu, Kai-Hui Chang, Dylan Dobbyn, Sy-Yen Kuo. 1494-1499 [doi]
- Optimizing equivalence checking for behavioral synthesisKecheng Hao, Fei Xie, Sandip Ray, Jin Yang. 1500-1505 [doi]
- Checking and deriving module paths in Verilog cell library descriptionsMatthias Raffelsieper, Mohammad Reza Mousavi, Chris W. H. Strolenberg. 1506-1511 [doi]
- BACH 2 : Bounded reachability checker for compositional linear hybrid systemsLei Bu, You Li, Linzhang Wang, Xin Chen, Xuandong Li. 1512-1517 [doi]
- DVFS based task scheduling in a harvesting WSN for Structural Health MonitoringA. Ravinagarajan, D. Dondi, Tajana Simunic Rosing. 1518-1523 [doi]
- Power-accuracy tradeoffs in human activity transition detectionJeffrey Boyd, Hari Sundaram, Aviral Shrivastava. 1524-1529 [doi]
- Non-invasive blood oxygen saturation monitoring for neonates using reflectance pulse oximeterWei Chen, Idowu Ayoola, Sidarto Bambang-Oetomo, Loe M. G. Feijs. 1530-1535 [doi]
- An active vision system for fall detection and posture recognition in elderly healthcareGiovanni Diraco, Alessandro Leone, Pietro Siciliano. 1536-1541 [doi]
- A Smart Space application to dynamically relate medical and environmental informationFabio Vergari, Sara Bartolini, Federico Spadini, Alfredo D Elia, Guido Zamagni, Luca Roffia, Tullio Salmon Cinotti. 1542-1547 [doi]
- An architecture for self-organization in pervasive systemsAly A. Syed, Johan Lukkien, Roxana Frunza. 1548-1553 [doi]
- TIMBER: Time borrowing and error relaying for online timing error resilienceMihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken. 1554-1559 [doi]
- ERSA: Error Resilient System Architecture for probabilistic applicationsLarkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. Jacobson, Subhasish Mitra. 1560-1565 [doi]
- Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processorsLei Zhang 0008, Yue Yu, Jianbo Dong, Yinhe Han, Shangping Ren, Xiaowei Li. 1566-1571 [doi]
- Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessorsPramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson. 1572-1577 [doi]
- Robust design of embedded systemsMartin Lukasiewycz, Michael Glaß, Jürgen Teich. 1578-1583 [doi]
- Energy-efficient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraintLin Huang, Qiang Xu. 1584-1589 [doi]
- PM-COSYN: PE and memory co-synthesis for MPSoCsYi-Jung Chen, Chia-Lin Yang, Po-Han Wang. 1590-1595 [doi]
- Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCsBrett H. Meyer, Adam S. Hartman, Donald E. Thomas. 1596-1601 [doi]
- Efficient power conversion for ultra low voltage micro scale energy transducersChao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy. 1602-1607 [doi]
- Transmitting TLM transactions over analogue wire modelsStephan Schulz, Jörg Becker, Thomas Uhle, Karsten Einwich, Sören Sonntag. 1608-1613 [doi]
- Intent-leveraged optimization of analog circuits via homotopyMetha Jeeradit, Jaeha Kim, Mark Horowitz. 1614-1619 [doi]
- Panel: Reliability of data centers: Hardware vs. softwareMehdi Baradaran Tahoori, Ishwar Parulkar, Dan Alexandrescu, Kevin Granlund, Allan Silburt, Bapi Vinnakota. 1620 [doi]
- Optimal regulation of traffic flows in networks-on-chipFahimeh Jafari, Zhonghai Lu, Axel Jantsch, Mohammad Hossien Yaghmaee. 1621-1624 [doi]
- A method to remove deadlocks in Networks-on-Chips with Wormhole flow controlCiprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli. 1625-1628 [doi]
- An analytical method for evaluating Network-on-Chip performanceSahar Foroutan, Yvain Thonnart, Richard Hersemeule, Ahmed Jerraya. 1629-1632 [doi]
- A low-area flexible MIMO detector for WiFi/WiMAX standardsNariman Moezzi Madani, Thorlindur Thorolfsson, William Rhett Davis. 1633-1636 [doi]
- An embedded wide-range and high-resolution CLOCK jitter measurement circuitYu Lee, Ching-Yuan Yang, Nai-Chen Daniel Cheng, Ji-Jan Chen. 1637-1640 [doi]
- Analog circuit test based on a digital signatureA. Gomez, R. Sanahuja, L. Balado, Joan Figueras. 1641-1644 [doi]
- DAGS: Distribution agnostic sequential Monte Carlo scheme for task execution time estimationNabeel Iqbal, M. A. Siddique, Jörg Henkel. 1645-1648 [doi]
- Taming the component timing: A CBD methodology for real-time embedded systemsManoj G. Dixit, Pallab Dasgupta, S. Ramesh. 1649-1652 [doi]
- Deterministic, predictable and light-weight multithreading using PRET-CSidharta Andalam, Partha S. Roop, Alain Girault. 1653-1656 [doi]
- Inversed Temperature Dependence aware clock skew scheduling for sequential circuitsJieyi Long, Seda Ogrenci Memik. 1657-1660 [doi]
- DynAHeal: Dynamic energy efficient task assignment for wireless healthcare systemsPriti Aghera, Dilip Krishnaswamy, Diana Fang, Ayse Coskun, Tajana Rosing. 1661-1664 [doi]
- Instruction precomputation with memoization for fault detectionDemid Borodin, Ben H. H. Juurlink. 1665-1668 [doi]
- Simultaneous budget and buffer size computation for throughput-constrained task graphsMaarten Wiggers, Marco Bekooij, Marc Geilen, Twan Basten. 1669-1672 [doi]
- An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuitsXiaoda Pan, Fan Yang, Xuan Zeng, Yangfeng Su. 1673-1676 [doi]
- Panel session - great challenges in nanoelectronics and impact on academic research: More than Moore or Beyond CMOS?R. De Keersmaeker, M. Roukes, D. Antoinadis, H. De Man, G. Bourianoff, M. Brillouet, L. Samuelson. 1677 [doi]
- 3D-integration of silicon devices: A key technology for sophisticated productsArmin Klumpp, Peter Ramm, R. Wieland. 1678-1683 [doi]
- Creating 3D specific systems: Architecture, design and CADPaul D. Franzon, W. Rhett Davis, Thor Thorolffson. 1684-1688 [doi]
- Testing TSV-based three-dimensional stacked ICsErik Jan Marinissen. 1689-1694 [doi]
- Leveraging dominators for preprocessing QBFHratch Mangassarian, Bao Le, Alexandra Goultiaeva, Andreas G. Veneris, Fahiem Bacchus. 1695-1700 [doi]
- Formal specification of networks-on-chips: deadlock and evacuationFreek Verbeek, Julien Schmaltz. 1701-1706 [doi]
- Tighter integration of BDDs and SMT for Predicate AbstractionAlessandro Cimatti, Anders Franzén, Alberto Griggio, Krishnamani Kalyanasundaram, Marco Roveri. 1707-1712 [doi]
- An HVS-based Adaptive Computational Complexity Reduction Scheme for H.264/AVC video encoder using Prognostic Early Mode ExclusionMuhammad Shafique, Bastian Molkenthin, Jörg Henkel. 1713-1718 [doi]
- Scheduling and energy-distortion tradeoffs with operational refinement of image processingDavide Anastasia, Yiannis Andreopoulos. 1719-1724 [doi]
- enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoderMuhammad Shafique, Lars Bauer, Jörg Henkel. 1725-1730 [doi]
- A method for design of impulse bursts noise filters optimized for FPGA implementationsZdenek Vasícek, Lukás Sekanina, Michal Bidlo. 1731-1736 [doi]
- Exploration of hardware sharing for image encodersSebastián López, Roberto Sarmiento, Philip G. Potter, Wayne Luk, Peter Y. K. Cheung. 1737-1742 [doi]
- Towards hardware stereoscopic 3D reconstruction a real-time FPGA computation of the disparity mapS. Hadjitheophanous, C. Ttofis, A. S. Georghiades, Theocharis Theocharides. 1743-1748 [doi]
- A robust ADC code hit counting techniqueJiun-Lang Huang, Kuo-Yu Chou, Ming-Huan Lu, Xuan-Lun Huang. 1749-1754 [doi]
- An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial linksMohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada. 1755-1760 [doi]
- Fault diagnosis of analog circuits based on machine learningKe Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir. 1761-1766 [doi]
- Block-level bayesian diagnosis of analogue electronic circuitsShaji Krishnan, Klaas D. Doornbos, Rudi Brand, Hans G. Kerkhoff. 1767-1772 [doi]
- Control network generator for latency insensitive designsEliyah Kilada, Kenneth S. Stevens. 1773-1778 [doi]
- Using Speculative Functional Units in high level synthesisAlberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Román Hermida, Seda Ogrenci Memik. 1779-1784 [doi]
- Retiming multi-rate DSP algorithms to meet real-time requirementXue-Yang Zhu. 1785-1790 [doi]
- Combining optimizations in automated low power designQiang Liu, Tim Todman, Wayne Luk. 1791-1796 [doi]
- A new quaternary FPGA based on a voltage-mode multi-valued circuitCristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro. 1797-1802 [doi]
- An evaluation of a slice fault aware tool chainAdwait Gupte, Phillip Jones. 1803-1808 [doi]
- Reliability- and process variation-aware placement for FPGAsAssem A. M. Bsoul, Naraig Manjikian, Li Shang. 1809-1814 [doi]