Table of Contents

• CANSim: When to Utilize Synchronous and Asynchronous Routers in Large and Complex NoCsTom Glint, Manu Awasthi, Joycee Mekie. 1-6 [doi]
• PAIR: Periodically Alternate the Identity of Routers to Ensure Deadlock Freedom in NoCZifeng Zhao, Xinghao Zhu, Jiyuan Bai, Gengsheng Chen. 7-12 [doi]
• SCNoCs: An Adaptive Heterogeneous Multi-NoC with Selective Compression and Power GatingFan Jiang, Chengeng Li, Lin Chen, Jiaqi Liu, Wei Zhang, Jiang Xu. 13-18 [doi]
• QuadraNet: Improving High-Order Neural Interaction Efficiency with Hardware-Aware Quadratic Neural NetworksChenhui Xu, Fuxun Yu, Zirui Xu, Chenchen Liu, Jinjun Xiong, Xiang Chen 0010. 19-25 [doi]
• RobustDiCE: Robust and Distributed CNN Inference at the EdgeXiaotian Guo, Quan Jiang, Andy D. Pimentel, Todor P. Stefanov. 26-31 [doi]
• YoseUe: "trimming" Random Forest's training towards resource-constrained inferenceAlessandro Verosimile, Alessandro Tierno, Andrea Damiani, Marco D. Santambrogio. 32-37 [doi]
• P2LSG: Powers-of-2 Low-Discrepancy Sequence Generator for Stochastic ComputingMehran Shoushtari Moghadam, Sercan Aygun, Mohsen Riahi Alam, M. Hassan Najafi. 38-45 [doi]
• PAAP-HD: PIM-Assisted Approximation for Efficient Hyper-Dimensional ComputingFangxin Liu, Haomin Li, Ning Yang, Yichi Chen, Zongwu Wang, Tao Yang, Li Jiang. 46-51 [doi]
• FPGA-Based HPC for Associative Memory SystemDeyu Wang, Yuning Wang, Yu Yang, Dimitrios Stathis 0001, Ahmed Hemani, Anders Lansner, Jiawei Xu 0002, Li-Rong Zheng 0001, Zhuo Zou. 52-57 [doi]
• Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet IntegrationFuping Li, Ying Wang 0001, Yujie Wang, Mengdi Wang, Yinhe Han 0001, Huawei Li 0001, Xiaowei Li 0001. 58-64 [doi]
• CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICsBangqi Fu, Lixin Liu, Yang Sun, Wing Ho Lau, Martin D. F. Wong, Evangeline F. Y. Young. 65-70 [doi]
• O.O: Optimized One-die Placement for Face-to-face Bonded 3D ICsXingyu Tong, Zhijie Cai, Peng Zou, Min Wei, Yuan Wen, Zhifeng Lin, Jianli Chen. 71-76 [doi]
• iEDA: An Open-source infrastructure of EDAXingquan Li, Zengrong Huang, Simin Tao, Zhipeng Huang 0009, Chunan Zhuang, Hao Wang, Yifan Li, Yihang Qiu, Guojie Luo, Huawei Li 0001, Haihua Shen, Mingyu Chen 0001, Dongbo Bu, Wenxing Zhu, Ye Cai, Xiaoming Xiong, Ying Jiang, Yi Heng, Peng Zhang 0007, Bei Yu 0001, Biwei Xie, Yungang Bao. 77-82 [doi]
• iPD: An Open-source intelligent Physical Design ToolchainXingquan Li, Simin Tao, Shijian Chen, Zhisheng Zeng, Zhipeng Huang 0009, Hongxi Wu, Weiguo Li, Zengrong Huang, Liwei Ni, Xueyan Zhao, He Liu, Shuaiying Long, Ruizhi Liu, Xiaoze Lin, Bo Yang, Fuxing Huang, Zonglin Yang, Yihang Qiu, Zheqing Shao, Jikang Liu, Yuyao Liang, Biwei Xie, Yungang Bao, Bei Yu 0001. 83-88 [doi]
• A Resource-efficient Task Scheduling System using Reinforcement Learning : Invited PaperChedi Morchdi, Cheng-Hsiang Chiu, Yi Zhou 0017, Tsung-Wei Huang. 89-95 [doi]
• Machine Learning and GPU Accelerated Sparse Linear Solvers for Transistor-Level Circuit Simulation: A Perspective Survey (Invited Paper)Zhou Jin 0001, Wenhao Li, Yinuo Bai, Tengcheng Wang, Yicheng Lu, Weifeng Liu 0002. 96-101 [doi]
• HomeSGN: A Smarter Home with Novel Rule Mining Enabled by a Scorer-Generator GANZehua Yuan, Junhao Pan, Xiaofan Zhang 0001, Deming Chen. 102-108 [doi]
• Adaptive Workload Distribution for Accuracy-aware DNN Inference on Collaborative Edge PlatformsZain Taufique, Antonio Miele, Pasi Liljeberg, Anil Kanduri. 109-114 [doi]
• Extending Neural Processing Unit and Compiler for Advanced Binarized Neural NetworksMinjoon Song, Faaiz Asim, Jongeun Lee. 115-120 [doi]
• JustQ: Automated Deployment of Fair and Accurate Quantum Neural NetworksRuhan Wang, Fahiz Baba-Yara, Fan Chen 0001. 121-126 [doi]
• Using Boolean Satisfiability for Exact Shuttling in Trapped-Ion Quantum ComputersDaniel Schönberger, Stefan Hillmich, Matthias Brandl, Robert Wille. 127-133 [doi]
• Optimizing Decision Diagrams for Measurements of Quantum CircuitsRyosuke Matsuo, Rudy Raymond, Shigeru Yamashita, Shin-ichi Minato. 134-139 [doi]
• CTQr: Control and Timing-Aware Qubit RoutingChing-Yao Huang, Wai-Kei Mak. 140-145 [doi]
• BNN-Flip: Enhancing the Fault Tolerance and Security of Compute-in-Memory Enabled Binary Neural Network AcceleratorsAkul Malhotra, Chunguang Wang, Sumeet Kumar Gupta. 146-152 [doi]
• ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise PatternsYiming Chen, Guodong Yin, Hongtao Zhong, Mingyen Lee, Huazhong Yang, Sumitha George, Vijaykrishnan Narayanan, Xueqing Li. 153-158 [doi]
• A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory AcceleratorsYuan-Chun Luo, James Read, Anni Lu, Shimeng Yu. 159-164 [doi]
• Design of Aging-Robust Clonable PUF Using an Insulator-Based ReRAM for Organic CircuitsKunihiro Oshima, Kazunori Kuribara, Takashi Sato. 165-170 [doi]
• Heterogeneous Graph Attention Network Based Statistical Timing Library Characterization with Parasitic RC ReductionXu Cheng, Yuyang Ye, Guoqing He, Qianqian Song, Peng Cao. 171-176 [doi]
• An Optimization-aware Pre-Routing Timing Prediction Framework Based on Heterogeneous Graph LearningGuoqing He, Wenjie Ding, Yuyang Ye, Xu Cheng, Qianqian Song, Peng Cao. 177-182 [doi]
• BoCNT: A Bayesian Optimization Framework for Global CNT Interconnect OptimizationHang Wu, Ning Xu, Wei W. Xing, Yuanqing Cheng. 183-188 [doi]
• Timing Analysis beyond Complementary CMOS Logic StylesJan Lappas, Mohamed Amine Riahi, Christian Weis, Norbert Wehn, Sani R. Nassif. 189-194 [doi]
• Collaborative Coalescing of Redundant Memory Access for GPU SystemFan Jiang, Chengeng Li, Wei Zhang, Jiang Xu. 195-200 [doi]
• WER: Maximizing Parallelism of Irregular Graph Applications Through GPU Warp EqualizeREn-Ming Huang, Bo-Wun Cheng, Meng-Hsien Lin, Chun-Yi Lee, Tsung Tai Yeh. 201-206 [doi]
• SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC DesignShixin Chen, Su Zheng, Chen Bai, Wenqian Zhao, Shuo Yin, Yang Bai, Bei Yu 0001. 207-212 [doi]
• ARS-Flow: A Design Space Exploration Flow for Accelerator-rich System based on Active LearningShuaibo Huang, Yuyang Ye, Hao Yan 0002, Longxing Shi. 213-218 [doi]
• Secco: Codesign for Resource Sharing in Regular-Expression AcceleratorsJackson Woodruff, Sam Ainsworth, Michael F. P. O'Boyle. 219-224 [doi]
• SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network AccelerationChen Yin, Jianfei Jiang 0001, Qin Wang 0009, Zhigang Mao, Naifeng Jing. 225-230 [doi]
• APoX: Accelerate Graph-Based Deep Point Cloud Analysis via Adaptive Graph ConstructionLei Dai, Shengwen Liang, Ying Wang 0001, Huawei Li 0001, Xiaowei Li 0001. 231-237 [doi]
• FuseFPS: Accelerating Farthest Point Sampling with Fusing KD-tree Construction for Point CloudsMeng Han, Liang Wang, Limin Xiao, Hao Zhang, Chenhao Zhang, Xilong Xie, Shuai Zheng, Jin Dong. 238-243 [doi]
• A Fixed-Point Pre-Processing Hardware Architecture Design for Complex Independent Component AnalysisYashwant Moses, Madhav Rao. 244-249 [doi]
• Pearls Hide Behind Linearity: Simplifying Deep Convolutional Networks for Embedded Hardware Systems via Linearity GraftingXiangzhong Luo, Di Liu 0002, Hao Kong, Shuo Huai, Hui Chen 0016, Shiqing Li, Guochu Xiong, Weichen Liu. 250-255 [doi]
• On Decomposing Complex Test Cases for Efficient Post-silicon ValidationC. Harshitha, Sundarapalli Harikrishna, Peddakotla Rohith, Sandeep Chandran, Rajshekar Kalayappan. 256-261 [doi]
• DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause PredictionGuangyu Hu, Jianheng Tang, Changyuan Yu, Wei Zhang 0012, Hongce Zhang. 262-268 [doi]
• TIUP: Effective Processor Verification with Tautology-Induced Universal PropertiesYufeng Li, Yiwei Ci, Qiusong Yang. 269-274 [doi]
• Verifying Embedded Graphics Libraries leveraging Virtual Prototypes and Metamorphic TestingChristoph Hazott, Florian Stögmüller, Daniel Große. 275-281 [doi]
• MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-MemorySimranjeet Singh, Chandan Kumar Jha 0001, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant. 282-287 [doi]
• An Effective Netlist Planning Approach for Double-sided Signal RoutingTzu-Chuan Lin, Fang-Yu Hsu, Wai-Kei Mak, Ting-Chi Wang. 288-293 [doi]
• An Analytical Placement Algorithm with Routing topology OptimizationMin Wei, Xingyu Tong, Zhijie Cai, Peng Zou, Zhifeng Lin, Jianli Chen. 294-299 [doi]
• Effective Analytical Placement for Advanced Hybrid-Row-Height Circuit DesignsYuan Wen, Benchao Zhu, Zhifeng Lin, Jianli Chen. 300-305 [doi]
• Row Planning and Placement for Hybrid-Row-Height DesignsChing-Yao Huang, Wai-Kei Mak. 306-311 [doi]
• TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based DesignChen-Hao Hsu, Xiaoqing Xu, Hao Chen 0059, Dino Ruic, David Z. Pan. 312-318 [doi]
• Towards Finding the Sources of Polymorphism in Polymorphic Gates (Invited)Timothy Dunlap, Zelin Lu, Gang Qu 0001. 319-324 [doi]
• HOGE: Homomorphic Gate on An FPGAKotaro Matsuoka, Song Bian 0001, Takashi Sato 0001. 325-332 [doi]
• Sensors for Remote Power Attacks: New Developments and ChallengesBrian Udugama, Darshana Jayasinghe, Sri Parameswaran. 333-340 [doi]
• PRESS: Persistence Relaxation for Efficient and Secure Data Sanitization on Zoned Namespace Storage : (Invited Paper)Yun-Shan Hsieh, Bo-Jun Chen, Po-Chun Huang, Yuan-Hao Chang 0001. 341-348 [doi]
• Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific KnowledgeWeimin Fu, Shijie Li, Yifang Zhao, Haocheng Ma, Raj Gautam Dutta, Xuan Zhang 0001, Kaichen Yang, Yier Jin, Xiaolong Guo. 349-354 [doi]
• FormalFuzzer: Formal Verification Assisted Fuzz Testing for SoC Vulnerability DetectionNusrat Farzana Dipu, Muhammad Monir Hossain, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor. 355-361 [doi]
• DeepIncept: Diversify Performance Counters with Deep Learning to Detect MalwareZhuoran Li, Dan Zhao. 362-367 [doi]
• Resource- and Workload-aware Malware Detection through Distributed Computing in IoT NetworksSreenitha Kasarapu, Sanket Shukla, Sai Manoj Pudukotai Dinakarrao. 368-373 [doi]
• APPLE: An Explainer of ML Predictions on Circuit Layout at the Circuit-Element LevelTao Zhang, Haoyu Yang, Kang Liu, Zhiyao Xie. 374-379 [doi]
• E2E-Check: End to End GPU-Accelerated Design Rule Checking with Novel Mask Boolean AlgorithmsYifei Zhou, Zijian Wang, Chao Wang. 380-385 [doi]
• CIS: Conditional Importance Sampling for Yield Optimization of Analog and SRAM CircuitsYanfang Liu, Wei W. Xing. 386-391 [doi]
• FineMap: A Fine-grained GPU-parallel LUT Mapping EngineTianji Liu, Lei Chen 0031, Xing Li, Mingxuan Yuan, Evangeline F. Y. Young. 392-397 [doi]
• Transduction Method for AIG MinimizationYukio Miyasaka. 398-403 [doi]
• In Medio Stat Virtus*: Combining Boolean and Pattern MatchingGianluca Radi, Alessandro Tempia Calvino, Giovanni De Micheli. 404-410 [doi]
• A Transferable GNN-based Multi-Corner Performance Variability Modeling for Analog ICsHongjian Zhou, Yaguang Li, Xin Xiong, Pingqiang Zhou. 411-416 [doi]
• An Efficient Transfer Learning Assisted Global Optimization Scheme for Analog/RF CircuitsZhikai Wang, Jingbo Zhou, Xiaosen Liu, Yan Wang 0023. 417-422 [doi]
• MACRO: Multi-agent Reinforcement Learning-based Cross-layer Optimization of Operational AmplifierZihao Chen, Songlei Meng, Fan Yang 0001, Li Shang, Xuan Zeng 0001. 423-428 [doi]
• FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Models : (Invited Paper)Ruiyang Qin, Yuting Hu, Zheyu Yan, Jinjun Xiong, Ahmed Abbasi, Yiyu Shi 0001. 429-434 [doi]
• Invited Paper: Software/Hardware Co-design for LLM and Its Application for Design VerificationLily Jiaxin Wan, Yingbing Huang, Yuhong Li, Hanchen Ye, Jinghua Wang, Xiaofan Zhang, Deming Chen. 435-441 [doi]
• wearMeter: an Accurate Wear Metric for NAND Flash MemoryMin Ye, Qiao Li 0001, Daniel Wen, Tei-Wei Kuo, Chun Jason Xue. 442-447 [doi]
• Overlapping Aware Zone Allocation for LSM Tree-Based Store on ZNS SSDsJingcheng Shen, Lang Yang, Linbo Long, Renping Liu, Zhenhua Tan, Congming Gao, Yi Jiang. 448-453 [doi]
• Hardware-Software Co-Design of a Collaborative DNN Accelerator for 3D Stacked Memories with Multi-Channel DataTom Glint, Manu Awasthi, Joycee Mekie. 454-459 [doi]
• Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge ArchitectureLiyan Chen, Jianfei Jiang 0001, Qin Wang 0009, Zhigang Mao, Naifeng Jing. 460-465 [doi]
• Variational Label-Correlation Enhancement for Congestion PredictionBiao Liu, Congyu Qiao, Ning Xu, Xin Geng, Ziran Zhu, Jun Yang. 466-471 [doi]
• Fast Cell Library Characterization for Design Technology Co-Optimization Based on Graph Neural NetworksTianliang Ma, Zhihui Deng, Xuguang Sun, Leilai Shao. 472-477 [doi]
• Automated synthesis of mixed-signal ML inference hardware under accuracy constraintsKishor Kunal, Jitesh Poojary, S. Ramprasath 0001, Ramesh Harjani, Sachin S. Sapatnekar. 478-483 [doi]
• LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design StageHye Rim Ji, Jong-Seong Kim, Jung Yun Choi, Jee-Hyong Lee 0001. 484-490 [doi]
• QcAssert: Quantum Device Testing with Concurrent AssertionsHasini Witharana, Daniel Volya, Prabhat Mishra 0001. 491-496 [doi]
• HybMT: Hybrid Meta-Predictor based ML Algorithm for Fast Test Vector GenerationShruti Pandey, Jayadeva, Smruti R. Sarangi. 497-502 [doi]
• A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT SolverZhiteng Chao, Xindi Zhang, Junying Huang, Jing Ye 0001, Shaowei Cai 0001, Huawei Li 0001, Xiaowei Li 0001. 503-508 [doi]
• A Dynamic Testing Scheme for Resistive-Based Computation-In-Memory ArchitecturesSina Bakhtavari Mamaghani, Priyanjana Pal, Mehdi Baradaran Tahoori. 509-514 [doi]
• SWAT: An Efficient Swin Transformer Accelerator Based on FPGAQiwei Dong, Xiaoru Xie, Zhongfeng Wang 0001. 515-520 [doi]
• TransFRU: Efficient Deployment of Transformers on FPGA with Full Resource UtilizationHongji Wang, Yueyin Bai, Jun Yu 0010, Kun Wang 0005. 521-526 [doi]
• Booth-NeRF: An FPGA Accelerator for Instant-NGP Inference with Novel Booth-MultiplierZihang Ma, ZeYu Li, Yuanfang Wang, Yu Li 0003, Jun Yu, Kun Wang. 527-532 [doi]
• ACane: An Efficient FPGA-based Embedded Vision Platform with Accumulation-as-Convolution Packing for Autonomous Mobile RobotsJinho Yang, Sungwoong Yune, Sukbin Lim, Donghyuk Kim, Joo-Young Kim 0001. 533-538 [doi]
• OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision ConfigurationYung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka. 539-544 [doi]
• BFP-CIM: Data-Free Quantization with Dynamic Block-Floating-Point Arithmetic for Energy-Efficient Computing-In-Memory-based AcceleratorCheng-Yang Chang, Chi-Tse Huang, Yu-Chuan Chuang, Kuang-Chao Chou, An-Yeu Andy Wu. 545-550 [doi]
• A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI ApplicationsLizhou Wu, Chenyang Zhao, Jingbo Wang, Xueru Yu, Shoumian Chen, Chen Li, Jun Han 0003, Xiaoyong Xue, Xiaoyang Zeng. 551-556 [doi]
• PRIMATE: Processing in Memory Acceleration for Dynamic Token-pruning TransformersYue Pan, Minxuan Zhou, Chonghan Lee, Zheyu Li, Rishika Kushwah, Vijaykrishnan Narayanan, Tajana Rosing. 557-563 [doi]
• Adaptive Control-Logic Routing for Fully Programmable Valve Array Biochips Using Deep Reinforcement LearningHuayang Cai, Genggeng Liu, Wenzhong Guo, Zipeng Li, Tsung-Yi Ho, Xing Huang. 564-569 [doi]
• Towards Automated Testing of Multiplexers in Fully Programmable Valve Array BiochipsGenggeng Liu, Yuqin Zeng, Yuhan Zhu, Huayang Cai, Wenzhong Guo, Zipeng Li, Tsung-Yi Ho, Xing Huang. 570-575 [doi]
• The Need for Speed: Efficient Exact Simulation of Silicon Dangling Bond LogicJan Drewniok, Marcel Walter, Robert Wille. 576-581 [doi]
• Towards Multiphase Clocking in Single-Flux Quantum SystemsRassul Bairamkulov, Giovanni De Micheli. 582-587 [doi]
• Algebraic and Boolean Methods for SFQ Superconducting CircuitsAlessandro Tempia Calvino, Giovanni De Micheli. 588-593 [doi]
• LOOPLock 3.0: A Robust Cyclic Logic Locking ApproachPei-pei Chen, Xiang-Min Yang, Yu-Cheng He, Yung-Chih Chen, Yi-Ting Li, Chun-Yao Wang. 594-599 [doi]
• Logic Locking over TFHE for Securing User Data and AlgorithmsKohei Suemitsu, Kotaro Matsuoka, Takashi Sato 0001, Masanori Hashimoto. 600-605 [doi]
• LIPSTICK: Corruptibility-Aware and Explainable Graph Neural Network-based Oracle-Less Attack on Logic LockingYeganeh Aghamohammadi, Amin Rezaei 0001. 606-611 [doi]
• Power Side-Channel Analysis and Mitigation for Neural Network Accelerators based on Memristive CrossbarsBrojogopal Sapui, Mehdi B. Tahoori. 612-617 [doi]
• Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled CircuitsKazuki Minamiguchi, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi. 618-624 [doi]
• SPIRAL: Signal-Power Integrity Co-Analysis for High-Speed Inter-Chiplet Serial Links ValidationXiao Dong, Songyu Sun, Yangfan Jiang, Jingtong Hu, Dawei Gao, Cheng Zhuo. 625-630 [doi]
• Nested Dissection Based Parallel Transient Power Grid Analysis on Public Cloud Virtual MachinesJiawen Cheng, Zhiqiang Liu, Lingjie Li, Wenjian Yu. 631-637 [doi]
• Efficient Sublogic-Cone-Based Switching Activity Estimation using Correlation FactorKexin Zhu, Runjie Zhang, Qing He. 638-643 [doi]
• ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine LearningHyunsu Chae, Keren Zhu 0001, Bhyrav Mutnury, Zixuan Jiang, Daniel De Araujo, Douglas Wallace, Douglas Winterberg, Adam R. Klivans, David Z. Pan. 644-650 [doi]
• Physics-Informed Learning for EPG-Based TDDB AssessmentDinghao Chen, Wenjie Zhu, Xiaoman Yang, Pengpeng Ren, Zhigang Ji, Hai-Bao Chen. 651-656 [doi]
• Toward End-to-End Analog Design Automation with ML and Data-Driven Approaches (Invited Paper)Supriyo Maji, Ahmet Faruk Budak, Souradip Poddar, David Z. Pan. 657-664 [doi]
• Reinforcing the Connection between Analog Design and EDA (Invited Paper)Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath 0001, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar. 665-670 [doi]
• A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper)Ruiyu Lyu, Yuan Meng, Aidong Zhao, Zhaori Bi, Keren Zhu 0001, Fan Yang 0001, Changhao Yan, Dian Zhou, Xuan Zeng 0001. 671-678 [doi]
• Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper)Peng Xu, Jintao Li, Tsung-Yi Ho, Bei Yu 0001, Keren Zhu 0001. 679-685 [doi]
• The Optimal Quantum of Temporal DecouplingNiko Zurstraßen, Ruben Brandhofer, José Cubero-Cascante, Nils Bosbach, Lukas Jünger 0001, Rainer Leupers. 686-691 [doi]
• Towards a Highly Interactive Design-Debug-Verification CycleLucas Klemmer, Daniel Große. 692-697 [doi]
• Beyond Time-Quantum: A Basic-Block FDA Approach for Accurate System Computing Performance EstimationHsuan-Yi Lin, Ren-Song Tsay. 698-703 [doi]
• BoostIID: Fault-agnostic Online Detection of WCET Changes in Autonomous DrivingSaehanseul Yi, Nikil D. Dutt. 704-709 [doi]
• KalmanHD: Robust On-Device Time Series Forecasting with Hyperdimensional ComputingIvannia Gomez Moreno, Xiaofan Yu, Tajana Rosing. 710-715 [doi]
• HyperFeel: An Efficient Federated Learning Framework Using Hyperdimensional ComputingHaomin Li, Fangxin Liu, Yichi Chen, Li Jiang. 716-721 [doi]
• RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language ModelYao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie. 722-727 [doi]
• LSTP: A Logic Synthesis Timing PredictorHaisheng Zheng, Zhuolun He, Fangzhou Liu, Zehua Pei, Bei Yu 0001. 728-733 [doi]
• Bridging the Design Methodologies of Burst-Mode Specifications and Signal Transition GraphsAlex Chan, Danil Sokolov, Victor Khomenko, Alex Yakovlev. 734-739 [doi]
• Signature Driven Post-Manufacture Testing and Tuning of RRAM Spiking Neural Networks for Yield RecoveryAnurup Saha, Chandramouli N. Amarnath, Kwondo Ma, Abhijit Chatterjee. 740-745 [doi]
• Physics-Informed Learning for Versatile RRAM Reset and Retention SimulationTianshu Hou, Yuan Ren, Wenyong Zhou, Can Li, Zhongrui Wang, Hai-Bao Chen, Ngai Wong. 746-751 [doi]
• Hard Error Correction in STT-MRAMSurendra Hemaram, Mehdi B. Tahoori, Francky Catthoor, Siddharth Rao, Sebastien Couet, Gouri Sankar Kar. 752-757 [doi]
• Exploiting 2.5D/3D Heterogeneous Integration for AI ComputingZhenyu Wang, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Yaotian Liu, Jae-sun Seo, Chaitali Chakrabarti, Ümit Y. Ogras, Vidya A. Chhabria, Jeff Zhang 0001, Yu Cao 0001. 758-764 [doi]
• Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous ChipletsZhuoping Yang, Shixin Ji, Xingzhen Chen, Jinming Zhuang, Weifeng Zhang, Dharmesh Jani, Peipei Zhou 0001. 765-770 [doi]
• Towards Automated Generation of Chiplet-Based Systems Invited PaperAnkur Limaye, Claudio Barone, Nicolas Bohm Agostini, Marco Minutoli, Joseph B. Manzano, Vito Giovanni Castellana, Giovanni Gozzi, Michele Fiorito, Serena Curzel, Fabrizio Ferrandi, Antonino Tumeo. 771-776 [doi]
• Flexible Spatio-Temporal Energy-Efficient Runtime ManagementRobert Khasanov, Marc Dietrich, Jerónimo Castrillón. 777-784 [doi]
• Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product DataflowYuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu. 785-791 [doi]
• Meeting Job-Level Dependencies by Task MergingMatthias Becker 0004. 792-798 [doi]
• A CGRA Front-end Compiler Enabling Extraction of General Control and Dedicated OperatorsXuchen Gao, Yunhui Qiu, Yuan Dai, Wenbo Yin, Lingli Wang. 799-804 [doi]
• LOSSS-Logic Synthesis based on Several Stateful logic gates for high time-efficient computingYihong Hu, Nuo Xu, Chaochao Feng, Wei Tong, Kang Liu, Liang Fang. 805-811 [doi]
• Towards Area-Efficient Path-Based In-Memory Computing using Graph IsomorphismsSven Thijssen, Muhammad Rashedul Haq Rashed, Hao Zheng 0005, Sumit Kumar Jha 0001, Rickard Ewetz. 812-817 [doi]
• READ-based In-Memory Computing using Sentential Decision DiagramsSven Thijssen, Muhammad Rashedul Haq Rashed, Sumit Kumar Jha 0001, Rickard Ewetz. 818-823 [doi]
• ConvFIFO: A Crossbar Memory PIM Architecture for ConvNets Featuring First-In-First-Out DataflowLiang Zhao, Yu Qian, Fanzi Meng, Xiapeng Xu, Xunzhao Yin, Cheng Zhuo. 824-829 [doi]
• MINT: Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural NetworksRuokai Yin, Yuhang Li, Abhishek Moitra, Priyadarshini Panda. 830-835 [doi]
• TQ-TTFS: High-Accuracy and Energy-Efficient Spiking Neural Networks Using Temporal Quantization Time-to-First-Spike NeuronYuxuan Yang, Zihao Xuan, Yi Kang. 836-841 [doi]
• TEAS: Exploiting Spiking Activity for Temporal-wise Adaptive Spiking Neural NetworksFangxin Liu, Haomin Li, Ning Yang, Zongwu Wang, Tao Yang, Li Jiang. 842-847 [doi]
• SOLSA: Neuromorphic Spatiotemporal Online Learning for Synaptic AdaptationZhenhang Zhang, Jingang Jin, Haowen Fang, Qinru Qiu. 848-853 [doi]
• Signed Convolution in Photonics with Phase-Change Materials using Mixed-Polarity BitstreamsRaphael Cardoso, Clément Zrounba, Mohab Abdalla, Paul Jiménez, Mauricio Gomes de Queiroz, Benoît Charbonnier, Fabio Pavanello, Ian O'Connor, Sébastien Le Beux. 854-859 [doi]
• An Efficient Branch-and-Bound Routing Algorithm for Optical NoCsYihao Liu 0006, Yaoyao Ye. 860-865 [doi]
• Boosting Graph Spectral Sparsification via Parallel Sparse Approximate Inverse of Cholesky FactorBaiyu Chen, Zhiqiang Liu, Yibin Zhang, Wenjian Yu. 866-871 [doi]
• Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit SizingXuyang Zhao, Zhaori Bi, Changhao Yan, Fan Yang 0001, Ye Lu, Dian Zhou, Xuan Zeng 0001. 872-877 [doi]
• Quantization-aware Optimization Approach for CNNs Inference on CPUsJiasong Chen, Zeming Xie, Weipeng Liang, Bosheng Liu, Xin Zheng, Jigang Wu, Xiaoming Xiong. 878-883 [doi]
• TSTC: Enabling Efficient Training via Structured Sparse Tensor CompilationShiyuan Huang, Fangxin Liu, Tian Li, Zongwu Wang, Haomin Li, Li Jiang. 884-889 [doi]
• An automated approach for improving the inference latency and energy efficiency of pretrained CNNs by removing irrelevant pixels with focused convolutionsCaleb Tung, Nicholas Eliopoulos, Purvish Jajal, Gowri Ramshankar, Cheng-Yun Yang, Nicholas Synovic, Xuecen Zhang, Vipin Chaudhary, George K. Thiruvathukal, Yung-Hsiang Lu. 890-895 [doi]
• PIONEER: Highly Efficient and Accurate Hyperdimensional Computing using Learned ProjectionFatemeh Asgarinejad, Justin Morris, Tajana Rosing, Baris Aksanli. 896-901 [doi]
• Logic Design of Neural Networks for High-Throughput and Low-Power ApplicationsKangwei Xu, Grace Li Zhang, Ulf Schlichtmann, Bing Li 0005. 902-907 [doi]
• Exact Scheduling to Minimize Off-Chip Data Movement for Deep Learning AcceleratorsYi Li, Aarti Gupta, Sharad Malik. 908-914 [doi]
• Run-time Non-uniform Quantization for Dynamic Neural Networks in Wireless CommunicationPriscilla Sharon Allwin, Manil Dev Gomony, Marc Geilen. 915-920 [doi]
• PipeFuser: Building Flexible Pipeline Architecture for DNN Accelerators via Layer FusionXilang Zhou, Shuyang Li, Haodong Lu, Kun Wang. 921-926 [doi]
• A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme EdgeLongwei Huang, Chao Fang, Qiong Li, Jun Lin 0001, Zhongfeng Wang 0001. 927-932 [doi]
• Microscope: Causality Inference Crossing the Hardware and Software Boundary from Hardware PerspectiveZhaoxiang Liu, Kejun Chen, Dean Sullivan, Orlando Arias, Raj Dutta, Yier Jin, Xiaolong Guo. 933-938 [doi]
• d-GUARD: Thwarting Denial-of-Service Attacks via Hardware Monitoring of Information Flow using Language Semantics in Embedded SystemsGarett Cunningham, Harsha Chenji, David Juedes, Avinash Karanth. 939-944 [doi]
• Security Coverage Metrics for Information Flow at the System LevelEce Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan 0002, Rolf Drechsler. 945-950 [doi]
• Theoretical Patchability Quantification for IP-Level Hardware Patching DesignsWei-Kai Liu, Benjamin Tan 0001, Jason M. Fung, Krishnendu Chakrabarty. 951-956 [doi]
• Multiplierless Design of High-Speed Very Large Constant MultiplicationsLevent Aksoy, Debapriya Basu Roy, Malik Imran, Samuel Pagliarini. 957-962 [doi]
• V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and ReroutingPing Zhang, Pengju Yao, Xingquan Li, Bei Yu 0001, Wenxing Zhu. 963-968 [doi]
• A Fast and Robust Global Router with Capacity Reduction TechniquesYun-Kai Fang, Ye-Chih Lin, Ting-Chi Wang. 969-974 [doi]
• A High Performance Detailed Router Based on Integer Programming with Adaptive Route GuidesZhongdong Qi, Shizhe Hu, Qi Peng, Hailong You, Chao Han, Zhangming Zhu. 975-980 [doi]