Abstract is missing.
- A Field Programmable Gate Array-Based Digital Temperature Sensor with Improved Immunity to Static Supply ShiftAkpojotor Princewill, Oluwatope Ayodeji, Ayodele Kayode, Aderounmu Adesola, Adagunodo Rotimi. 1-8 [doi]
- A Versatile Emulator for the Aging Effect of Non-volatile Memories: The Case of NAND FlashAntonios Prodromakis, Stelios Korkotsides, Theodore Antonakopoulos. 9-15 [doi]
- A Multiuser FBMC Receiver Implementation for Asynchronous Frequency Division Multiple AccessVincent Berg, Jean-Baptiste Dore, Dominique Noguet. 16-21 [doi]
- Design Space Exploration in an FPGA-Based Software Defined RadioMatthieu Gautier, Ganda Stephane Ouedraogo, Olivier Sentieys. 22-27 [doi]
- Systematic Exploration of Power-Aware Scenarios for IEEE 802.11ac WLAN SystemsNikolaos Zompakis, Iason Filippopoulos, Per Gunnar Kjeldsberg, Francky Catthoor, Dimitrios Soudris. 28-35 [doi]
- Flexible Radio Interface for NoC RF-InterconnectFrederic Drillet, Mohamad Hamieh, Lounis Zerioul, Alexandre Briere, Eren Unlu, Myriam Ariaudo, Yves Louet, Emmanuelle Bourdel, Julien Denoulet, Andréa Pinna, Bertrand Granado, Patrick Garda, François Pêcheux, Cedric Duperrier, Sébastien Quintanel, Philippe Meunier, Christophe Moy, Olivier Romain. 36-41 [doi]
- Morphable Compression Architecture for Efficient Configuration in CGRAsSyed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen. 42-49 [doi]
- Design Space Exploration for Customized Asymmetric Heterogeneous MPSoCBouthaina Damak, Rachid Benmansour, Mouna Baklouti, Smaïl Niar, Mohamed Abid. 50-57 [doi]
- Virtual Devices for Hot-Pluggable ProcessorsPierre Bomel, Kevin Martin, Jean-Philippe Diguet. 58-65 [doi]
- High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAsB. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan. 66-73 [doi]
- Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC ArchitecturesEricles Rodrigues Sousa, Deepak Gangadharan, Frank Hannig, Jürgen Teich. 74-81 [doi]
- Accelerating Volume Image Registration through Correlation Ratio Based Methods on GPUsAng Li, Akash Kumar. 82-89 [doi]
- Real-Time Digital Video Stabilization on an FPGALuis Araneda, Miguel Figueroa. 90-97 [doi]
- NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology NodesHalil Kukner, Pieter Weckx, Sebastien Morrison, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, Guido Groeseneken. 98-107 [doi]
- Critical Path Tracing Based Simulation of Transition Delay FaultsJaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik. 108-113 [doi]
- Closing the Gap between Speed and Configurability of Multi-bit Fault Emulation Environments for Security and Safety-Critical DesignsRalph Nyberg, Jurgen Nolles, Johann Heyszl, Dirk Rabe, Georg Sigl. 114-121 [doi]
- Development Framework for Model Driven Architecture to Accomplish Power-Aware Embedded SystemsManuel Menghin, Norbert Druml, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid. 122-128 [doi]
- Data-and State-Dependent Power Characterisation and Simulation of Black-Box RTL IP Components at System LevelDaniel Lorenz, Kim Grüttner, Wolfgang Nebel. 129-136 [doi]
- Adaptive Algorithm and Tool Flow for Accelerating System C on Many-Core ArchitecturesChristoph Roth, Simon Reder, Harald Bucher, Oliver Sander, Jürgen Becker. 137-145 [doi]
- A Time Synchronization Circuit with an Average 4.6 ns One-Hop Skew for Wired Wearable NetworksFardin Derogarian, João Canas Ferreira, Vitor M. Grade Tavares. 146-153 [doi]
- Design of an Embedded Health Monitoring Infrastructure for Accessing Multi-processor SoC DegradationYong Zhao, Hans G. Kerkhoff. 154-160 [doi]
- Generating On-Chip Heterogeneous Systems from High-Level Parallel CodeAlessandro Cilardo, Luca Gallo. 161-168 [doi]
- Designing and Evaluating High Speed Elliptic Curve Point MultipliersApostolos P. Fournaris, John Zafeirakis, Odysseas G. Koufopavlou. 169-174 [doi]
- Efficient Multiplication on Low-Resource DevicesWolfgang Wieser, Michael Hutter. 175-182 [doi]
- AHEMS: Asynchronous Hardware-Enforced Memory SafetyKuan-Yu Tseng, Dao Lu, Zbigniew Kalbarczyk, Ravishankar K. Iyer. 183-190 [doi]
- ParaDIME: Parallel Distributed Infrastructure for Minimization of EnergySanthosh Kumar Rethinagiri, Oscar Palomar, Anita Sobe, Thomas Knauth, Wojciech M. Barczynski, Gulay Yalcin, Yarco Hayduk, Adrián Cristal, Osman S. Unsal, Pascal Felber, Christof Fetzer, Julien Ryckaert, Gina Alioto. 191-198 [doi]
- Cross-Layer Early Reliability Evaluation for the Computing cOntinuumStefano Di Carlo, Alessandro Vallero, Dimitris Gizopoulos, Giorgio Di Natale, Arnaud Grasset, Riccardo Mariani, Frank Reichenbach. 199-205 [doi]
- EUROSERVER: Energy Efficient Node for European Micro-ServersYves Durand, Paul M. Carpenter, Stefano Adami, Angelos Bilas, Denis Dutoit, Alexis Farcy, Georgi Gaydadjiev, John Goodacre, Manolis Katevenis, Manolis Marazakis, Emil Matús, Iakovos Mavroidis, John Thomson. 206-213 [doi]
- P-SOCRATES: A Parallel Software Framework for Time-Critical Many-Core SystemsLuís Miguel Pinho, Eduardo Quiñones, Marko Bertogna, Andrea Marongiu, Jorge Pereira Carlos, Claudio Scordino, Michele Ramponi. 214-221 [doi]
- Gigasample Time-Interleaved Delta-Sigma Modulator for FPGA-Based All-Digital TransmittersRui Fiel Cordeiro, Arnaldo S. R. Oliveira, Jose Vieira, Nelson V. Silva. 222-227 [doi]
- Instruction Folding Compression for Java Card Runtime EnvironmentMassimiliano Zilli, Wolfgang Raschke, Reinhold Weiss, Johannes Loinig, Christian Steger. 228-235 [doi]
- Anytime System Level Verification via Random Exhaustive Hardware in the Loop SimulationToni Mancini, Federico Mari, Annalisa Massini, Igor Melatti, Enrico Tronci. 236-245 [doi]
- Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System SoftwareMarkus Becker, Christoph Kuznik, Wolfgang Mueller. 246-253 [doi]
- Towards Component-Based Design of Safety-Critical Cyber-Physical ApplicationsAlejandro Masrur, Michal Kit, Tomás Bures, Wolfram Hardt. 254-261 [doi]
- Simulation Alternatives for Modeling Networked Cyber-Physical SystemsMichele Lora, Riccardo Muradore, Riccardo Reffato, Franco Fummi. 262-269 [doi]
- A High Performance Java Card Virtual Machine Interpreter Based on an Application Specific Instruction-Set ProcessorMassimiliano Zilli, Wolfgang Raschke, Reinhold Weiss, Johannes Loinig, Christian Steger. 270-278 [doi]
- Compression of Lookup Table for Piecewise Polynomial Function EvaluationShen-Fu Hsiao, Chia-Sheng Wen, Po-Han Wu. 279-284 [doi]
- Composable and Predictable Dynamic Loading for Time-Critical Partitioned SystemsShubhendu Sinha, Martijn Koedam, Rob van Wijk, Andrew Nelson, Ashkan Beyranvand Nejad, Marc Geilen, Kees G. W. Goossens. 285-292 [doi]
- End-to-End Real-Time Communication in Mixed-Criticality Systems Based on Networked Multicore ChipsRoman Obermaisser, Zaher Owda, Mohammed Abuteir, Hamidreza Ahmadian, Donatus Weber. 293-302 [doi]
- Iterative FPGA Implementation Easing Safety Certification for Mixed-Criticality Embedded Real-Time SystemsDaniel Münch, Michael Paulitsch, Michael Honold, Wolfgang Schlecker, Andreas Herkersdorf. 303-311 [doi]
- The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical ApplicationsJakub Podivinsky, Ondrej Cekan, Marcela Simková, Zdenek Kotásek. 312-319 [doi]
- Fault Tolerant Duplex System with High Availability for Practical ApplicationsPavel Vit, Jaroslav Borecky, Martin Kohlík, Hana Kubatova. 320-325 [doi]
- Automatic Construction of On-line Checking Circuits Based on Finite AutomataLucie Matuova, Jan Kastil, Zdenek Kotásek. 326-332 [doi]
- Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental FrameworkJosef Strnadel, Martin Pokorny. 333-340 [doi]
- Properties of Dynamically Dead Instructions for Contemporary ArchitecturesMarianne J. Jantz, Katherine Wu, Prasad A. Kulkarni. 341-348 [doi]
- Improving Power of Cache and Register File through Critical Path InstructionsKuangLun Chen, Ehsan Atoofian, Ali Manzak. 349-355 [doi]
- Stochastic Logic Realization of Matrix OperationsPai-Shun Ting, John Patrick Hayes. 356-364 [doi]
- Ultra Low-Power Computation via Graphene-Based Adiabatic Logic GatesSandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino. 365-371 [doi]
- A Flexible and Lightweight ECC-Based Authentication Solution for Resource Constrained SystemsNorbert Druml, Manuel Menghin, Adnan Kuleta, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid. 372-378 [doi]
- Voltage Glitch Attacks on Mixed-Signal SystemsNoemie Beringuier-Boher, Kamil Gomina, David Hély, Jean-Baptiste Rigaud, Vincent Beroulle, Assia Tria, Joel Damiens, Philippe Gendrier, Philippe Candelier. 379-386 [doi]
- Seesaw: An Area-Optimized FPGA Viterbi Decoder for PUFsMatthias Hiller, Leandro Rodrigues Lima, Georg Sigl. 387-393 [doi]
- A Safety Certification Strategy for IEC-61508 Compliant Industrial Mixed-Criticality Systems Based on Multicore PartitioningJon Perez, David Gonzalez, Carlos Fernando Nicolas, Ton Trapman, Jose Miguel Garate. 394-400 [doi]
- Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor ArchitectureLeonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Ian Broster, Francisco J. Cazorla. 401-410 [doi]
- 2-SPP Approximate Synthesis for Error Tolerant ApplicationsAnna Bernasconi, Valentina Ciriani. 411-418 [doi]
- Three-Dimensional Design Space Exploration for System Level SynthesisShuo Li, Ahmed Hemani. 419-426 [doi]
- On Robustness of EDA ToolsJan Schmidt, Petr Fiser, Jiri Balcarek. 427-434 [doi]
- Communication-Driven Automatic Virtual Prototyping for Networked Embedded SystemsLiyuan Zhang, Joachim Falk, Tobias Schwarzer, Michael Glaß, Jürgen Teich. 435-442 [doi]
- Automatic Synthesis over Multiple APIs from Uml/Marte Models for Easy Platform Mapping and ReuseAlejandro Nicolás, Pablo Peñil, Héctor Posadas, Eugenio Villar. 443-450 [doi]
- Design Techniques for NCL-Based Asynchronous Circuits on Commercial FPGAMatthew M. Kim, Paul Beckett. 451-458 [doi]
- Architecture of Effective High-Speed Network Stream MergerPavel Benácek, Hana Kubatova, Viktor Pus. 459-464 [doi]
- Parameterized AES-Based Crypto Processor for FPGAsHassan Anwar, Masoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila, Hannu Tenhunen, Sergei Dytckov, Giovanni Beltrame. 465-472 [doi]
- Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS CircuitsAlexandru Amaricai, Sergiu Nimara, Oana Boncalo, Jiaoyan Chen, Emanuel M. Popovici. 473-479 [doi]
- A Fault Attack Emulation Environment to Evaluate Java Card Virtual-Machine SecurityMichael Lackner, Reinhard Berlach, Michael Hraschan, Reinhold Weiss, Christian Steger. 480-487 [doi]
- Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-FlopsUsman Khalid, Antonio Mastrandrea, Mauro Olivieri. 488-495 [doi]
- Efficient STDP Micro-Architecture for Silicon Spiking Neural NetworksSergei Dytckov, Masoud Daneshtalab, Masoumeh Ebrahimi, Hassan Anwar, Juha Plosila, Hannu Tenhunen. 496-503 [doi]
- Flexible Virtual Channel Power-Gating for High-Throughput and Low-Power Network-on-ChipFeng Wang, Xiantuo Tang, Qinglin Wang, Zuocheng Xing, Hengzhu Liu. 504-511 [doi]
- Ultra-Small Designs for Inversion-Based S-BoxesMarkus Stefan Wamser. 512-519 [doi]
- Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis AttacksPartha De, Kunal Banerjee, Chittaranjan A. Mandal, Debdeep Mukhopadhyay. 520-527 [doi]
- Emission Analysis of Hardware ImplementationsShahin Tajik, Dmitry Nedospasov, Clemens Helfmeier, Jean-Pierre Seifert, Christian Boit. 528-534 [doi]
- An Elliptic Curve Crypto-Processor Secured by Randomized WindowsSimon Pontie, Paolo Maistri, Régis Leveugle. 535-542 [doi]
- HOG Feature Extractor Hardware Accelerator for Real-Time Pedestrian DetectionMaryam Hemmati, Morteza Biglari-Abhari, Stevan Berber, Smaïl Niar. 543-550 [doi]
- Design and Implementation of Multiple-Vehicle Detection and Tracking Systems with Machine LearningShen-Fu Hsiao, Guan-Fu Yeh, Je-Chi Chen. 551-558 [doi]
- A Tiny Scale VLIW Processor for Real-Time Constrained Embedded Control TasksOliver Stecklina, Michael Methfessel. 559-566 [doi]
- An Efficient Approach for Soft Error Rate Estimation of Combinational CircuitsMohsen Raji, Fereshte Saeedi, Behnam Ghavami, Hossein Pedram. 567-574 [doi]
- Design of Fault-Secure Transposed FIR Filters Protected Using Residue CodesStanislaw J. Piestrak, Piotr Patronik. 575-582 [doi]
- On Enhancing Fault Injection's Capabilities and Performances for Safety Critical SystemsStefano Di Carlo, Giulio Gambardella, Paolo Prinetto, Frank Reichenbach, Trond Løkstad, Gulzaib Rafiq. 583-590 [doi]
- Comparison of Enhanced Markov Models and Discrete Event Simulation: For Evaluation of Probabilistic Faults in Safety-Critical Real-Time Task SetsStefan Kramer, Peter Raab, Jürgen Mottok, Stanislav Racek. 591-598 [doi]
- Improving Coverage of Simulation-Based Verification by Dedicated Stimuli GenerationShuo Yang, Robert Wille, Rolf Drechsler. 599-606 [doi]
- Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDAMahdi Jelodari Mamaghani, Jim D. Garside, William B. Toms, Doug A. Edwards. 607-614 [doi]
- Many-Core Scheduling of Data Parallel Applications Using SMT SolversPranav Tendulkar, Peter Poplavko, Ioannis Galanommatis, Oded Maler. 615-622 [doi]
- Accuracy Improvement of Dataflow Analysis for Cyclic Stream Processing Applications Scheduled by Static Priority Preemptive SchedulersPhilip S. Wilmanns, Joost P. H. M. Hausmans, Stefan J. Geuns, Marco Jan Gerrit Bekooij. 623-630 [doi]
- Fault-Tolerant Irregular Topology Design Method for Network-on-ChipsSuleyman Tosun, Vahid Babaei Ajabshir, Ozge Mercanoglu, Özcan Özturk. 631-634 [doi]
- Fast System Level Benchmarks for Multicore ArchitecturesAlper Sen 0001, Gokcehan Kara, Etem Deniz, Smaïl Niar. 635-638 [doi]
- A New Rounding Method Based on Parallel Remainder Estimation for Goldschmidt and Newton-Raphson AlgorithmsDaniel Piso Fernandez, Javier Diaz Bruguera. 639-642 [doi]
- Efficient High Speed Implementation of Secure Hash Algorithm-3 on Virtex-5 FPGAMuzaffar Rao, Thomas Newe, Ian Grout. 643-646 [doi]
- Multi-channel Raw-Data Acquisition for Ultrasound ResearchEnrico Boni, Andrea Cellai, Alessandro Ramalli, Matteo Lenge, Stefano Ricci. 647-650 [doi]
- Design Space Exploration for Automotive E/E Architecture Component PlatformsSebastian Graf, Michael Glaß, Jürgen Teich, Christoph Lauer. 651-654 [doi]
- Towards Exploring Vast MPSoC Mapping Design Spaces Using a Bias-Elitist Evolutionary ApproachWei Quan, Andy D. Pimentel. 655-658 [doi]
- Verification of Robotic Surgery Tasks by Reachability Analysis: A Comparison of ToolsDavide Bresolin, Luca Geretti, Riccardo Muradore, Paolo Fiorini, Tiziano Villa. 659-662 [doi]
- A 130 nm Event-Driven Voltage and Temperature Insensitive Capacitive ROCAlessia Damilano, Marco Crepaldi, Paolo Motto Ros, Danilo Demarchi. 663-666 [doi]
- Noodle: A Heuristic Algorithm for Task Scheduling in MPSoC ArchitecturesMuhammad Khurram Bhatti, Isil Oz, Ananya Muddukrishna, Konstantin Popov, Mats Brorsson. 667-670 [doi]
- Low-Power Differential Logic Gates for DPA Resistant CircuitsErica Tena-Sanchez, Javier Castro-Ramirez, Antonio J. Acosta. 671-674 [doi]
- FPGA Trojan Detection Using Length-Optimized Ring OscillatorsParis Kitsos, Artemios G. Voyiatzis. 675-678 [doi]
- PBO-Based Test CompressionJiri Balcarek, Petr Fiser, Jan Schmidt. 679-682 [doi]
- Design of a Redundant FPGA-Based Safety System for Railroad VehiclesDavid Macii, Manuel Avancini, Luigi Benciolini, Stefano Dalpez, Michele Corrà, Roberto Passerone. 683-686 [doi]
- Enhancing the Simulation-Centric Design of Cyber-Physical and Multi-physics Systems through Co-simulationAlessandro Beghi, Fabio Marcuzzi, Mirco Rampazzo, Marco Virgulin. 687-690 [doi]
- Majority Logic Synthesis for Spin Wave TechnologyOdysseas Zografos, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Praveen Raghavan, Giovanni De Micheli. 691-694 [doi]
- Design and Implementation of an Efficient Fingerprint Features ExtractorG. Vitello, Vincenzo Conti, Antonio Gentile, Salvatore Vitabile, Filippo Sorbello. 695-699 [doi]
- Prospeckz-5 - A Wireless Sensor Platform for Tracking and Monitoring of Wild HorsesJanek Mann, Ion Emilian Radoi, D. K. Arvind. 700-703 [doi]
- State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control SystemKarel Szurman, Lukas Miculka, Zdenek Kotásek. 704-707 [doi]
- Minimizing Reversible Circuits in the 2n Scheme Using Two and Three Bits PatternsMartin Lukac, Maher Hawash, Michitaka Kameyama, Marek A. Perkowski, Pawel Kerntopf. 708-711 [doi]