Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino. A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. In International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan. pages 73-76, IEEE, 2005. [doi]
Abstract is missing.