Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino. A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. In International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan. pages 73-76, IEEE, 2005. [doi]
@inproceedings{ItohTSNTM05,
title = {A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure},
author = {Niichi Itoh and Yasumasa Tsukamoto and Takeshi Shibagaki and Koji Nii and Hidehiro Takata and Hiroshi Makino},
year = {2005},
doi = {10.1109/ISCAS.2005.1464527},
url = {http://dx.doi.org/10.1109/ISCAS.2005.1464527},
researchr = {https://researchr.org/publication/ItohTSNTM05},
cites = {0},
citedby = {0},
pages = {73-76},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan},
publisher = {IEEE},
}