Chia-Tsun Wu - researchr alias

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Viewing Publication 1 - 4 from 4

2010

A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation AlgorithmChia-Tsun Wu, Wen-Chung Shen, Wei Wang, An-Yeu Wu. tcas, 57-II(6):430-434, 2010. [doi]

2006

A portable all-digital pulsewidth control loop for SOC applicationsWei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu. iscas 2006: [doi]

A frequency estimation algorithm for ADPLL designs with two-cycle lock-in timeChia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu. iscas 2006: [doi]

2005

A scalable DCO design for portable ADPLL designsChia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu. iscas 2005: 5449-5452 [doi]

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