A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm

Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, An-Yeu Wu. A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm. IEEE Trans. on Circuits and Systems, 57-II(6):430-434, 2010. [doi]

Abstract

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