T. Srikanthan - researchr alias

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Viewing Publication 1 - 9 from 9

2005

Elimination of sign precomputation in flat CORDICS. Suchitra, S. Sukthankar, T. Srikanthan, C. T. Clarke. iscas 2005: 3319-3322 [doi]

2003

A VLSI architecture for 3-D self-organizing map based color quantization and its FPGA implementationN. Sudha, T. Srikanthan, Babu Mailachalam. jsa, 48(11-12):337-352, 2003. [doi]

2002

Incorporating area-time flexibility to a binary signed-digit adderS. K. Lam, T. Srikanthan, N. Goyal, N. Tyagi. apccas 2002: 485-489 [doi]

A linear approximation based hybrid approach for binary logarithmic conversionS. K. Lam, T. Srikanthan. mam, 26(8):353-361, 2002. [doi]

Area-time issues in the VLSI implementation of self organizing map neural networksBabu Mailachalam, T. Srikanthan. mam, 26(9-10):399-406, 2002. [doi]

2000

A Robust Parallel Architecture for Adaptive Color QuantizationBabu Mailachalam, T. Srikanthan. itcc 2000: 164-173 [doi]

1999

VLSI Costs of Arithmetic Parallelism: A Residue Reverse Conversion PerspectivM. Bhardwaj, T. Srikanthan, C. T. Clarke. arith 1999: 176 [doi]

A Reverse Converter for the 4-moduli Superset {2^n-1, 2^n, 2^n+1, 2^(n+1)+1}M. Bhardwaj, T. Srikanthan, C. T. Clarke. arith 1999: 168-175 [doi]

Residue-to-binary arithmetic converter for moduli set {2n -1, 2n, 2n+1, 2n+1 -1}Jimson Mathew, D. Radhakrishnan, T. Srikanthan. nsip 1999: 185-188

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