Abstract is missing.
- Computer Arithmetic - A Programmer s PerspectiveRichard P. Brent. 2 [doi]
- New Algorithms for Improved Transcendental Functions on IA-64Shane Story, Ping Tak Peter Tang. 4-11 [doi]
- A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector ExtensionMartin S. Schmookler, Michael Putrino, Anh Mather, Jon Tyler, Huy Van Nguyen, Charles Roth, Mukesh Sharma, Mydung N. Pham, Jeff Lent. 12 [doi]
- Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand AdditionDhananjay S. Phatak, Israel Koren. 22-29 [doi]
- A Family of AddersSimon Knowles. 30-34 [doi]
- Reduced Latency IEEE Floating-Point Standard Adder ArchitecturesAndrew Beaumont-Smith, Neil Burgess, S. Lefrere, Cheng-Chew Lim. 35 [doi]
- On the Design of High-Radix On-Line Division for Long PrecisionAlexandre F. Tenca, Milos D. Ercegovac. 44-51 [doi]
- Boosting Very-High Radix Division with Prescaling and Selection by RoundingPaolo Montuschi, Tomás Lang. 52-59 [doi]
- Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16Alberto Nannarelli, Tomás Lang. 60 [doi]
- Montgomery Modular Exponentiation on Reconfigurable HardwareThomas Blum. 70-77 [doi]
- Moduli for Testing Implementations of the RSA CryptosystemColin D. Walter. 78-85 [doi]
- Digit-Recurrence Algorithm for Computing Euclidean Norm of a 3-D VectorNaofumi Takagi, Seiji Kuwahara. 86 [doi]
- Correctness Proofs Outline for Newton-Raphson Based Floating-Point Divide and Square Root AlgorithmsMarius A. Cornea-Hasegan, Roger A. Golliver, Peter W. Markstein. 96-105 [doi]
- Floating Point Division and Square Root Algorithms and Implementation in the AMD-K7 MicroprocessorStuart F. Oberman. 106-115 [doi]
- Series Approximation Methods for Divide and Square Root in the Power3(TM) ProcessorMartin S. Schmookler, Ramesh C. Agarwal, Fred G. Gustavson. 116-123 [doi]
- High-Speed Inverse Square RootsMichael J. Schulte, Kent E. Wires. 124 [doi]
- Arithmetic with Signed Analog DigitsAryan Saed, Majid Ahmadi, Graham A. Jullien. 134-141 [doi]
- A 32-Bit Logarithmic Arithmetic Unit and its Performance Compared to Floating-PointJohn N. Coleman, E. I. Chester. 142-151 [doi]
- Necessary and Sufficient Conditions for Parallel, Constant Time Conversion and AdditionPeter Kornerup. 152 [doi]
- Efficient VLSI Implementation of Modulo (2^n=B11) Addition and MultiplicationReto Zimmermann. 158-167 [doi]
- A Reverse Converter for the 4-moduli Superset {2^n-1, 2^n, 2^n+1, 2^(n+1)+1}M. Bhardwaj, T. Srikanthan, C. T. Clarke. 168-175 [doi]
- VLSI Costs of Arithmetic Parallelism: A Residue Reverse Conversion PerspectivM. Bhardwaj, T. Srikanthan, C. T. Clarke. 176 [doi]
- Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC AlgorithmJavier Hormigo, Julio Villalba, Emilio L. Zapata. 186-193 [doi]
- Complex Logarithmic Number System Arithmetic Using High-Radix Redundant CORDIC AlgorithmsDavid Lewis. 194-203 [doi]
- Very-High Radix CORDIC Vectoring with Scalings and Selection by RoundingElisardo Antelo, Tomás Lang, Javier D. Bruguera. 204 [doi]
- Area x Delay (A T) Efficient Multiplier Based on an Intermediate Hybrid Signed-Digit (HSD-1) RepresentationJeng-Jong J. Lue, Dhananjay S. Phatak. 216-224 [doi]
- A Comparison of Three Rounding Algorithms for IEEE Floating-Point MultiplicationGuy Even, Peter-Michael Seidel. 225-232 [doi]
- On Infinitely Precise Rounding for Division, Square Root, Reciprocal and Square Root ReciprocalCristina Iordache, David W. Matula. 233-240 [doi]
- Number-Theoretic Test Generation for Directed RoundingMichael Parks. 241 [doi]
- Multiplications of Floating Point ExpansionsMarc Daumas. 250-257 [doi]
- The S/390 G5 Floating Point Unit Supporting Hex and Binary ArchitecturesEric M. Schwarz, Ronald M. Smith, Christopher A. Krygowski. 258-265 [doi]
- Floating-Point Unit in Standard Cell Design with 116 Bit Wide DataflowGuenter Gerwig, Michael Kroener. 266 [doi]