A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders - researchr publication

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Stephen Bates, Gary Block. A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders. In International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan. pages 336-339, IEEE, 2005. [doi]

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