Stephen Bates, Gary Block. A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders. In International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan. pages 336-339, IEEE, 2005. [doi]
@inproceedings{BatesB05,
title = {A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders},
author = {Stephen Bates and Gary Block},
year = {2005},
doi = {10.1109/ISCAS.2005.1464593},
url = {http://dx.doi.org/10.1109/ISCAS.2005.1464593},
tags = {architecture},
researchr = {https://researchr.org/publication/BatesB05},
cites = {0},
citedby = {0},
pages = {336-339},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan},
publisher = {IEEE},
}