A memory controller that reduces latency of cached SDRAM

Seiji Miura, Satoru Akiyama. A memory controller that reduces latency of cached SDRAM. In International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan. pages 5250-5253, IEEE, 2005. [doi]

Abstract

Abstract is missing.