Dipankar Pal - researchr alias

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Viewing Publication 1 - 19 from 19

2023

IP Transformation Initiatives to Generate Scalable Functional Verification Collaterals for Smart Reusability and Reduced Effort for Sign-offSurajit Bhattacherjee, Dipankar Pal. iccnc 2023: 626-629 [doi]

2022

Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplierAloke Saha, Rakesh Kumar Singh, Dipankar Pal. mj, 119:105318, 2022. [doi]

2021

Novel All-Pass Section for High-Performance Signal Processing Using CMOS DCCIITaaha Nizam, V. Vijay, A. Srinivasulu, Dipankar Pal. tencon 2021: 7-10 [doi]

Efficient ternary comparator on CMOS technologyAloke Saha, Narendra Deo Singh, Dipankar Pal. mj, 109:105005, 2021. [doi]

2020

ASIC Implementation of High-Speed Adaptive Recursive Karatsuba Multiplier with Square-Root-Carry-Select-AdderAkhilesh G. Naik, Debarshi Deka, Dipankar Pal. lascas 2020: 1-4 [doi]

2019

RF Harvesting System for Low-Power Applications Using FinFETsT. Nagateja, Avireni Srinivasulu, Dipankar Pal. iccel 2019: 1-6 [doi]

2018

Secured and Imperceptible Data Transmission Through Digital Audio Signal with Reduced Internal NoiseDipankar Pal, Nabin Ghoshal. wpc, 100(2):505-518, 2018. [doi]

Delay estimation, chip-power analyses and comparison of single-level and multi-level recursive vedic algorithm with conventional algorithms for digital multiplierDipankar Pal, Akhilesh G. Naik. icicdt 2018: 29-32 [doi]

Modified Time-Based Current Mode ADCSuparno Pal, Dipankar Pal. tencon 2018: 1342-1345 [doi]

2017

CCII+ based dual square-and-triangular waveform generatorAvireni Srinivasulu, Dipankar Pal. ecai2 2017: 1-6 [doi]

2014

A Low Power 8-Bit Asynchronous SAR ADC Design Using Charge Scaling DACAnush Bekal, Manish Goswami, B. R. Singh, Dipankar Pal. ised 2014: 219-223 [doi]

2013

Low-power 6-GHz wave-pipelined 8b x 8b multiplierAloke Saha, Dipankar Pal, Mahesh Chandra. iet-cds, 7(3), 2013. [doi]

2010

A wide-input linear range sub-threshold transconductor for sub-Hz filteringChutham Sawigun, Dipankar Pal, Andreas Demosthenous. iscas 2010: 1567-1570 [doi]

2009

Current Conveyor-Based Square/Triangular Waveform Generators With Improved LinearityDipankar Pal, Avireni Srinivasulu, Basab Bijoy Pal, Andreas Demosthenous, B. N. Das. tim, 58(7):2174-2180, 2009. [doi]

Novel Current-mode Waveform Generator with Independent Frequency and Amplitude ControlDipankar Pal, Avireni Srinivasulu, Manish Goswami. iscas 2009: 2946-2949 [doi]

2007

A low-voltage, low-power, high-linearity cmos four-quadrant analog multiplierChutham Sawigun, Andreas Demosthenous, Dipankar Pal. ecctd 2007: 751-754 [doi]

A low-power CMOS analog voltage buffer using compact adaptive biasingChutham Sawigun, Jirayuth Mahattanakul, Andreas Demosthenous, Dipankar Pal. ecctd 2007: 1-4 [doi]

2005

10-channel very low noise ENG amplifier system using CMOS technologyRobert Rieger, Dipankar Pal, John Taylor, Chris Clarke, Peter Langlois, Nick Donaldson. iscas 2005: 748-751 [doi]

Two preamplifiers for non-invasive on-chip recording of neural-signalsRobert Rieger, Dipankar Pal, John Taylor, Peter Langlois. iscas 2005: 2727-2730 [doi]

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