Deploying Artificial Intelligence in Design Verification to Accelerate IP/SoC Sign-off with Zero Escape

Surajit Bhattacherjee, Daksh Shah, Dipankar Pal. Deploying Artificial Intelligence in Design Verification to Accelerate IP/SoC Sign-off with Zero Escape. In 6th IEEE International Conference on AI Circuits and Systems, AICAS 2024, Abu Dhabi, United Arab Emirates, April 22-25, 2024. pages 477-481, IEEE, 2024. [doi]

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