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Delay estimation, chip-power analyses and comparison of single-level and multi-level recursive vedic algorithm with conventional algorithms for digital multiplier

Dipankar Pal, Akhilesh G. Naik. Delay estimation, chip-power analyses and comparison of single-level and multi-level recursive vedic algorithm with conventional algorithms for digital multiplier. In 2018 International Conference on IC Design & Technology, ICICDT 2018, Otranto, Italy, June 4-6, 2018. pages 29-32, IEEE, 2018. [doi]

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