Shigeto Tanaka - researchr alias

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Viewing Publication 1 - 3 from 3

2007

A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block ArchitectureHiroki Sakurai, Shigeto Tanaka, Yasuhiro Sugimoto. ieicet, 90-A(10):2272-2279, 2007. [doi]

2006

A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video ApplicationsYasuhiro Sugimoto, Yuji Gohda, Shigeto Tanaka. ieicet, 89-C(6):811-813, 2006. [doi]

2005

The realization of a mismatch-free and 1.5-bit over-sampling pipelined ADCShigeto Tanaka, Yuji Gohda, Yasuhiro Sugimoto. iscas 2005: 6194-6197 [doi]

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