Hwang-Cherng Chow - researchr alias

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Viewing Publication 1 - 17 from 17

2022

Complex Human Activities Recognition Based on High Performance 1D CNN ModelRaman Maurya, T. Hui Teo, Shi Hui Chua, Hwang-Cherng Chow, I-Chyn Wey. mcsoc 2022: 330-336 [doi]

2017

A Simple Drain Current Model for MOS Transistors with the Lorentz Force EffectHwang-Cherng Chow, Prasenjit Chatterjee, Wu-Shiung Feng. sensors, 17(6):1199, 2017. [doi]

2016

Drain Current Modulation of a Single Drain MOSFET by Lorentz Force for Magnetic Sensing ApplicationPrasenjit Chatterjee, Hwang-Cherng Chow, Wu-Shiung Feng. sensors, 16(9):1389, 2016. [doi]

2014

Wide bandwidth and high precision power supply noise detector by using dual peak detection sample and hold circuitsI-Chyn Wey, Chien-Chang Peng, Hwang-Cherng Chow. ijcta, 42(5):529-541, 2014. [doi]

2008

A Low Voltage Rail-to-Rail OPAMP Design for Biomedical Signal Filtering ApplicationsHwang-Cherng Chow, Pu-Nan Weng. delta 2008: 232-235 [doi]

A high performance peak detector sample and hold circuit for detecting power supply noiseHwang-Cherng Chow, Zhi-Hau Hor. apccas 2008: 672-675 [doi]

2007

1V 10-bit successive approximation ADC for low power biomedical applicationsHwang-Cherng Chow, Yi-Hung Chen. ecctd 2007: 196-199 [doi]

High CMRR instrumentation amplifier for biomedical applicationsHwang-Cherng Chow, Jia-Yu Wang. isspa 2007: 1-4 [doi]

2005

A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applicationsHwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng. iscas 2005: 736-739 [doi]

2004

High performance sense amplifier circuit for low power SRAM applicationsHwang-Cherng Chow, Shu-Hsien Chang. iscas 2004: 741-744

2003

A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adderHwang-Cherng Chow, I-Chyn Wey. iscas 2003: 121-124 [doi]

2002

New pixel-shared design and split-path readout of CMOS image sensor circuitsHwang-Cherng Chow, Yung-Kuo Ho. iscas 2002: 49-52 [doi]

High performance automatic gain control circuit using a S/H peak-detector for ASK receiverHwang-Cherng Chow, I-Hsin Wang. icecsys 2002: 429-432 [doi]

A 3.3 V 1 GHz high speed pipelined Booth multiplierHwang-Cherng Chow, I-Chyn Wey. iscas 2002: 457-460 [doi]

2000

Novel output buffer designs for universal serial bus IC applicationsHwang-Cherng Chow, Chen-Yi Huang, Chih-Hong Chang. icecsys 2000: 3-6 [doi]

1999

Bidirectional buffer for mixed voltage applicationsHwang-Cherng Chow. iscas 1999: 270-273 [doi]

Duty cycle control circuit and applications to frequency dividersHwang-Cherng Chow. icecsys 1999: 1619-1622 [doi]

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